Datasheet

MAX11626
MAX11627
(4 CHANNELS)
MAX11628
MAX11629
(8 CHANNELS)
MAX11632
MAX11633
(16 CHANNELS)
NAME FUNCTION
5, 6, 7 — — N.C. No Connection. Not internally connected.
— — 1–15 AIN0–AIN14 Analog Inputs
— 1–7 — AIN0–AIN6 Analog Inputs
1–4 — — AIN0–AIN3 Analog Inputs
— — 16 CNVST/AIN15
Active-Low Conversion Start Input/Analog Input 15.
See Table 3 for details on programming the setup
register.
— 8 — CNVST/AIN7
Active-Low Conversion Start Input/Analog Input 7.
See Table 3 for details on programming the setup
register.
8 — — CNVST
Active-Low Conversion Start Input. See Table 3 for
details on programming the setup register.
9 9 17 REF
Reference Input. Bypass to GND with a 0.1µF
capacitor.
10 10 18 GND Ground
11 11 19 V
DD
Power Input. Bypass to GND with a 0.1µF capacitor.
12 12 20 CS
Active-Low Chip-Select Input. When CS is low, the
serial interface is enabled. When CS is high, DOUT
is high impedance.
13 13 21 SCLK
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See
Table 3 for details on programming the clock mode.
14 14 22 DIN
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
15 15 23 DOUT
Serial Data Output. Data is clocked out on the falling
edge of SCLK. High impedance when CS is connected
to V
DD
.
16 16 24 EOC
End of Conversion Output. Data is valid after EOC
pulls low.
MAX11626–MAX11629/
MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
www.maximintegrated.com
Maxim Integrated │ 10
Pin Description