Datasheet

MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
5
Maxim Integrated
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
Serial-Clock Frequency
f
SCLH
(Note 14) 1.7
MHz
Hold Time, Repeated START
Condition (Sr)
t
HD
,
STA
160
ns
Low Period of the SCL Clock t
LOW
320
ns
High Period of the SCL Clock t
HIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160
ns
Data Hold Time
t
HD
,
DAT
(Note 11) 0 150 ns
Data Setup Time
t
SU
,
DAT
10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
- 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
- 0.7V
DD
(Note 12) 20 160 ns
Setup Time for STOP (P) Condition
t
SU
,
STO
160
ns
Capacitive Load for Each Bus Line
C
B
400 pF
Pulse Width of Spike Suppressed
t
SP
(Notes 11 and 14) 0 10 ns
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
DD
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
REF
= 2.048V
(MAX11613/MAX11615/MAX11617), V
REF
= 4.096V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at V
DD
= 5V and the
MAX11613/MAX11615/MAX11617are tested at V
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit ).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Measured as for the MAX11613/MAX11615/MAX11617:
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
36 27
21
36 27
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