Datasheet

MAX1153/MAX1154
Stand-Alone, 10-Channel, 10-Bit System Monitors
with Internal Temperature Sensor and V
DD
Monitor
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 AIN0 Analog Voltage Input/Temperature Input Channel 0 or Positive Differential Input Relative to AIN1
2 AIN1 Analog Voltage Input/Temperature Input Channel 1 or Negative Differential Input Relative to AIN0
3 AIN2 Analog Voltage Input/Temperature Input Channel 2 or Positive Differential Input Relative to AIN3
4 AIN3 Analog Voltage Input/Temperature Input Channel 3 or Negative Differential Input Relative to AIN2
5 AIN4 Analog Voltage Input/Temperature Input Channel 4 or Positive Differential Input Relative to AIN5
6 AIN5 Analog Voltage Input/Temperature Input Channel 5 or Negative Differential Input Relative to AIN4
7 AIN6 Analog Voltage Input/Temperature Input Channel 6 or Positive Differential Input Relative to AIN7
8 AIN7 Analog Voltage Input/Temperature Input Channel 7 or Negative Differential Input Relative to AIN6
9 REF
Positive Reference Input in External Mode. Bypass REF with a 0.1μF capacitor to GND when in external mode.
When using the internal reference, REF must be left open.
10 INT Interrupt Output. Push-pull or open drain with selectable polarity. See Table 9 and the INT Interrupt Output section.
11 DOUT Serial Data Output. DOUT transitions on the falling edge of SCLK. High impedance when CS is at logic high.
12 GND Ground
13 V
DD
Positive Power Supply. Bypass V
DD
with a 0.1μF capacitor to GND.
14 DIN Serial Data Input. DIN data is latched into the serial interface on the rising edge of the SCLK.
15 SCLK Serial Clock Input. SCLK clocks data in and out of the serial interface (duty cycle must be 40% to 60%).
16 CS
Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high
impedance, and the serial interface resets.
ACCUMULATOR
INTERNAL TEMP
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
V
DD
/2
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN0
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN1
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN2
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN3
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN4
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN5
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN6
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN7
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
V
DD
MUX
TEMP
SENSOR
REFERENCE
12-BIT
ADC WITH
T/H
SCAN
AND
CONVERSION
CONTROL
POR
POWER
GOOD
INPUT CHANNEL REGISTER
INPUT CONFIGURATION REGISTER
STEP-UP REGISTER
ALARM REGISTER
AVERAGING
DIGITAL
COMPARATOR
SERIAL
INTERFACE
REF
DOUT
DIN
SCLK
INT
CS
MAX1153
MAX1154
Block Diagram