Datasheet

MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
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SCLK
DOUT
CS
SCK
MISO
V
DD
SS
QSPI
MAX1146–
MAX1149
CS
Figure 17. QSPI Connections
SCK
SDI
GND GND
I/O
SCLK
DOUT
V
DD
V
DD
MAX1146–
MAX1149
PIC16/PIC17
CS
Figure 18. SPI Interface Connection for a PIC16/PIC17
Controller
CONTROL BIT
PICI6/PICI7
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL Bit 7 X Write collision detection bit.
SSPOV Bit 6 X Receive overflow detect bit.
SSPEN Bit 5 1
Synchronous serial port enable bit:
0: Disables serial port and configures these pins as I/O port pins.
1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al - p or t p i ns.
CKP Bit 4 0 Clock polarity select bit. CKP = 0 for SPI master mode selection.
SSPM3 Bit 3 0
SSPM2 Bit 2 0
SSPM1 Bit 1 0
SSPM0 Bit 0 1
Synchronous serial port mode select bit. Sets SPI master mode and selects
F
CLK
= f
OSC
/ 16.
Table 8. Detailed SSPCON Register Content
CONTROL BIT
MAX1146–MAX1149
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP Bit 7 0
SPI data input sample phase. Input data is sampled at the middle of the data
output time.
CKE Bit 6 1
SPI clock edge select bit. Data is transmitted on the rising edge of the serial
clock.
D/A Bit 5 X Data address bit.
P Bit 4 X Stop bit.
S Bit 3 X Start bit.
R/W Bit 2 X Read/write bit information.
UA Bit 1 X Update address.
BF Bit 0 X Buffer full status bit.
Table 9. Detailed SSPSTAT Register Content