Datasheet
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
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Applications Information
Idle Mode
The device is considered idle when all the bits have been
clocked out or 18 zeros have been clocked in on DIN.
Start Bit
The falling edge of CS alone does not start a conver-
sion. The first logic high clocked into DIN with CS low is
interpreted as a start bit and defines the first bit of the
control byte. The device begins to track on the fifth
falling edge of SCLK after a start bit has been recog-
nized. A conversion starts on the eighth falling edge of
SCLK as the last bit of the control byte is being clocked
in. The start bit is defined as follows:
1) The first high bit clocked into DIN with CS low any
time the converter is idle.
or
2) The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto DOUT
(Figures 10 and 11).
Toggling CS before the current conversion is complete
aborts the conversion and clears the output register.
The fastest the MAX1146–MAX1149 can run with CS held
low between conversions is 18 clocks per conversion.
Figures 10 and 11 show the serial-interface timing neces-
sary to perform a conversion every 18 SCLK cycles.
SCLK
SSTRB
DIN
START
SEL2
SEL1 SEL0
PD1
PD0
18916 24
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS CONTROL BYTE SET TO CB1
TRACK
TRACKHOLD
HIGH-Z
DOUT
t
ACQ
HIGH-Z
t
CONV
CB1
OPEN
RESET TO CB1
D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0D7
CS
SGL/DIF
UNI/BIP
Figure 9. Internal Clock Mode Timing—24 Clocks/Conversion Timing
SCLK
SSTRB
DIN
START
SEL2
SEL1
SEL0
PD1 PD0
18
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS
CONTROL BYTE
TRACK
HOLD
DOUT
HIGH-Z
14
TRACK
10 1811
HOLD
14
D13 D12
10
D5 D4
11
SET TO CB2
SET TO CB1
START
SEL2
SEL1
SEL0
PD1
PD0
D13 D12 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0
START
SEL2
SEL1
SEL0
15
HOLD
CS
CB1 CB2
t
ACQ
t
CONV
t
ACQ
SGL/DIF
UNI/BIP UNI/BIP
SGL/DIF
UNI/BIP
SGL/DIF
Figure 10. External Clock Mode—18 Clocks/Conversion Timing