Datasheet
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
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Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1146–MAX1149 in internal
clock mode, making the MAX1146–MAX1149 ready to
convert with SSTRB high. No conversions should be
performed until the power supply is stable. The first log-
ical 1 on DIN with CS low is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, a rising edge on SCLK latches a bit from
DIN into the MAX1146–MAX1149 internal shift register.
After CS falls, the first logic 1 bit defines the control
byte’s MSB. Until this start bit arrives, any number of
logic 0 bits can be clocked into DIN with no effect.
Table 1 shows the control-byte format.
The MAX1146–MAX1149 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters. Set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI transmit a byte and receive a byte at the same
time. Using the Typical Application Circuit (Figure 4), the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the 14-bit conversion result).
SEL2
SEL1
SEL0
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
000+ -
100 + -
001 + -
101 + -
010 + -
110 + -
011 +-
111 +-
Table 2. MAX1148/MAX1149 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
000+-
001 +-
010 +-
011 +-
100- +
101 - +
110 - +
111 -+
Table 3. MAX1148/MAX1149 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
000+ -
100 + -
001 + -
101 +-
Table 4. MAX1146/MAX1147 Channel
Selection in Single-Ended Mode
(SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
000+-
001 +-
100-+
101 -+
Table 5. MAX1146/MAX1147 Channel
Selection in Differential Mode
(SGL/DIF = 0)