Datasheet

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
8
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= +1.8V to +3.6V, V
REF
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
REG
= 10µF, C
CPOUT
=
10µF, 10µF between CF+ and CF-, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DVDD Monitor Turn-On Time 5ms
CPOUT Monitor Supply Voltage
Range
1.0 3.6 V
CPOUT Monitor Trip Threshold 2.7 2.8 2.9 V
CPOUT Monitor Hysteresis 35 mV
CPOUT Monitor Turn-On Time 5ms
Internal Power-On Reset Voltage 1.7 V
32kHz Oscillator (32KIN, 32KOUT)
Clock Frequency V
DVDD
= 2.7V 32.768 kHz
Stability V
DVDD
= 1.8V to 3.6V, excluding crystal 25 ppm
Oscillator Startup Time 1500 ms
Crystal Load Capacitance 6pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)
Output Clock Frequency 32.768 kHz
Absolute Input to Output Clock
Jitter
Cycle to cycle 5 ns
Input to Output Rise/Fall Time 10% to 90%, 30pF load 5 ns
Input Duty Cycle 40 60 %
Output Duty Cycle 43 %
HIGH-FREQUENCY CLOCK OUTPUT (CLK)
f
OUT
= f
FLL
4.8660 4.9152 4.9644
f
OUT
= f
FLL
/2, power-up default 2.4330 2.4576 2.4822
f
OUT
= f
FLL
/4 1.2165 1.2288 1.2411
MHz
FLL Output Clock Frequency
f
OUT
= f
FLL
/8 608.25 614.4 620.54 kHz
Cycle to cycle, FLL off 0.15
Absolute Clock Jitter
Cycle to cycle, FLL on 1
ns
Rise and Fall Time t
R
/t
F
10% to 90%, 30pF load 10 ns
f
OUT
= 4.9152MHz 40 60
Duty Cycle
f
OUT
= 2.4576MHz, 1.2288MHz, 614.4kHz 45 55
%
Uncalibrated CLK Frequency
Error
FLL calibration not performed ±35 %
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)
Input High Voltage V
IH
0.7 x
V
DVDD
V
Input Low Voltage V
IL
0.3 x
V
DVDD
V