Datasheet

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
57
Maxim Integrated
INTERNAL
LOW DVDD DETECTOR
OUTPUT DISABLED,
BUT
PULLED LOW
OUTPUT ENABLED
SCLK,
DIN
CS
DOUT
INTERNAL
DRDY
UPIO(PWM)
CONNECTED TO POWER
SUPPLY SHDN PIN
INT
UPIO(SHDN)
UPIO(WU)
(INT. PULLUP)
CK32K
(32kHz)
SCK32E = 0
BUFFER DISABLED
CK32E = 1CK32E = 1
XIN, XOUT
(32kHz)
SOSCE = 1
OSCE = 1
OSCE = 1
POR
DVDD
1.8V
AVDD
1.8V
RESET
(OPEN-DRAIN)
INTERNAL EXTERNAL
INTERNAL
CRDY
HFCE = 1, FLLE = 1
CLK
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
0V
1
2
0V
1
2
LO
HI
LO
HI
LO
HI
SLEEP
WRITE
THREE-STATED
SPWME = 1
PWME = 0
PWME = 0
POWER SUPPLY OFF POWER SUPPLY OFF
t
DPU
t
DFI
t
DFI
INTERNAL
t
WU
t
DFON
t
DFON
t
DFOF
t
DPD
INTERNAL
IF FLLE = 0, CRDY WILL
STAY LOW, DFON = 0 )
INITIAL POWER, WAKE-UP, AND SLEEP
XTAL B/W 32KIN AND 32KOUT PIN
Figure 19. Initial Power-Up, Sleep Mode, and Wake-Up Timing Diagram with V
AVDD
> 1.8V