Datasheet
MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
50
Maxim Integrated
MODE
UP4MD<3:0>, UP3MD<3:0>,
UP2MD<3:0>, UP1MD<3:0>
MAX11359A
DESCRIPTION
0000 GPI
General-purpose digital input. Active edges detected by UPR_ or UPF_ status
register bits. ALH_ has no effect with this setting.
0001 GPO
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no effect with
this setting.
0010SWA or SWA
Digital input. DAC A buffer switch control. See the SWA bit description in the
SW_CTRL Register section.
0011 Reserved Reserved. Do not use these settings.
0100
SPDT1 or
SPDT1
D i g i tal i np ut. S P D T1 sw i tch contr ol . S ee the S P D T1< 1:0> b i t d escr i p ti on i n the
S W _C TRL Reg i ster secti on.
0101
SPDT2 or
SPDT2
D i g i tal i np ut. S P D T2 sw i tch contr ol . S ee the S P D T2< 1:0> b i t d escr i p ti on i n the
S W _C TRL Reg i ster secti on.
0110
SLEEP or
SLEEP
Sleep-mode digital input. Overrides power-control register and puts the part into
sleep mode when asserted. When deasserted, power mode is determined by the
SHDN bit.
0111WU or WU Wake-up digital input. Asserted edge clears SHDN bit.
1000
1001
1010
Reserved Reserved. Do not use these settings.
1011PWM or PWM
PWM digital output. Signal defined by the PWM_CTRL register. PWM on (or high or
“1”); assertion level defined by the ALH_ bit. When PWM is disabled (PWME = 0),
the UPIO pin idles high (DVDD or CPOUT) if ALH = 1, and low (DGND) if ALH = 0.
1100
SHDN or
SHDN
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on default of
GPI with pullup ensures initial power-supply turn-on when UPIO is connected to a
power supply with a SHDN input.
1101
AL_DAY or
AL_DAY
RTC alarm digital output. Asserts for time-of-day alarm events; equivalent to ALD in
STATUS register.
1110 Reserved Reserved. Do not use these settings.
1111DRDY or DRDY
ADC data-ready digital output. Asserts when analog-to-digital conversion or
calibration completes. Not masked by MADD bit.
Table 16. UPIO Mode Configuration
Note: When multiple UPIO inputs are configured for the same input function, the inputs are OR’ed together.