Datasheet

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
37
Maxim Integrated
The MUX register configures the positive and negative
mux inputs and can start an ADC conversion.
S (ADR0): Conversion start bit. The S bit is the LSB of
the MUX register address byte. S = 1 resets the regis-
ters inside the ADC filter and initiates a conversion or
calibration. The conversion begins immediately after
the eighth MUX register data bit, when S = 1 and when
writing to the MUX register. This allows the new MUX
and ADC register settings to take effect simultaneously
for a new conversion, if STRT = 0 during the last write
to the ADC register. If the S bit is asserted and the
command is a read from the MUX register, the conver-
sion starts immediately after the S bit (ADR0) is clocked
in by the rising edge of SCLK.
Read the MUX register with S = 1 for the fastest method
of initiating a conversion because only 8 bits are
required. The subsequent MUX register read is valid,
but can be aborted by raising CS with no harmful side
effects. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 and S = 1, the
ADC stops after a single conversion and holds the
result in the DATA register. If CONT = 1 and S = 1, the
ADC performs continuous conversions at the rate
specified by the RATE<2:0> bits until CONT deasserts
or ADCE deasserts, powering down the ADC. When a
conversion initiates using the S bit, the STRT bit asserts
and deasserts automatically after the initial conversion
completes. Writing to the MUX register with S = 0 caus-
es the MUX settings to change immediately and the
ADC continues in its prior state with its settings unaf-
fected. When the ADC is powered down, MUX inputs
are open.
MUXP<3:0>: MUX positive input bits. These four bits
select one of ten inputs from the positive MUX to go to the
positive output of the MUX as shown in Table 8. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
MUXN<3:0> MUX negative input bits. These four bits
select one of ten inputs from the negative MUX to go to
the negative output of the MUX as shown in Table 9. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
The DATA register contains the data from the most
recently completed conversion.
The OFFSET CAL register contains the 24-bit data of
the most recently completed offset calibration.
MSB LSB
S (ADR0) MUXP3 MUXP2 MUXP1 MUXP0 MUXN3 MUXN2 MUXN1 MUXN0
MUX Register (Power-On State: 0000 0000)
POSITIVE MUX
INPUT
MUXP3 MUXP2 MUXP1 MUXP0
AIN1 0 0 0 0
SNO1 0 0 0 1
FBA 0 0 1 0
SCM1 0 0 1 1
IN2- 0 1 0 0
SNC1 0 1 0 1
IN1- 0 1 1 0
TEMP+ 0 1 1 1
REF 1 0 0 0
AGND 1 0 0 1
101X
Open
11XX
Table 8. Selecting the Positive MUX Inputs
X = Don’t care.
NEGATIVE MUX
INPUT
MUXN3 MUXN2 MUXN1 MUXN0
TEMP- 0 0 0 0
SNO2 0 0 0 1
OUTA 0010
SCM2 0 0 1 1
OUT2 0 1 0 0
SNC2 0 1 0 1
OUT1 0 1 1 0
AIN2 0 1 1 1
REF 1000
AGND 1 0 0 1
101X
Open
11XX
Table 9. Selecting the Negative MUX Inputs
X = Don’t care.