Datasheet

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
36
Maxim Integrated
RATE<2:0>: ADC conversion-rate-setting bits. These
three bits set the conversion rate of the ADC as shown
in Table 6. The initial conversion requires four conver-
sion cycles for valid data, and subsequent conversions
require only one cycle (if CONT = 1). A full-scale input
change can require up to five cycles for valid data if
the digital filter is not reset with the STRT or S bit.
MODE<2:0>: Conversion-mode bits. These three bits
determine the type of conversion for the ADC as shown
in Table 7. When the ADC finishes an offset calibration
and/or gain calibration, the MODE<2:0> bits clear to 0
hex, the ADD bit in the STATUS register asserts, and
an interrupt asserts on INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked. Perform a gain calibra-
tion after achieving the desired offset (calibrated or
not). If an offset and gain calibration are performed
together (MODE<2:0> = 7 hex), the offset calibration is
performed first followed by the gain calibration, and the
µC is interrupted by INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked only upon completion of
both offset and gain calibration. After power-on or cali-
bration, the ADC does not begin conversions until initi-
ated by the user (see the ADCE and STRT bit
descriptions in this section and see the S bit descrip-
tions in the MUX Register section). See the GAIN CAL
Register and OFFSET CAL Register sections for details
on system calibration.
CONVERSION MODE MODE2 MODE1 MODE0
Normal 0 0 0
System Offset Calibration 0 0 1
System Gain Calibration 0 1 0
Normal 0 1 1
Normal 1 0 0
Self Offset Calibration 1 0 1
Self Gain Calibration 1 1 0
Self Offset and Gain
Calibration
111
Table 7. Setting the ADC Conversion Mode
NOMINAL
CONTINUOUS
CONVERSION
RATE (sps)
DECIMATION
RATIO
ACTUAL
CONTINUOUS
CONVERSION
RATE (sps)
10 1096 10.01042142
40 274 40.04168568
50 220 49.87009943
60 183 59.953125
200 55 199.4803977
240 46 238.5091712
400 27 406.3489583
512 23 477.0183424
CONTINUOUS
CONVERSION
RATE (sps)
SINGLE
CONVERSION
RATE (sps)
RATE2 RATE1 RATE0
10 2.5 0 0 0
40 10 0 0 1
50 12.5 0 1 0
60 15 0 1 1
200 50 1 0 0
240 60 1 0 1
400 100 1 1 0
512 128 1 1 1
Table 6a. Setting the ADC Conversion Rate*
*Calculate the ADC sampling rate using the following
equation:
where f
HFCLK
= 4.9152MHz nominally.
f
f
decimation ratio
S
HFCLK
=
×448
Table 6b. Actual ADC Conversion Rates