Datasheet

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
12
Maxim Integrated
TIMING CHARACTERISTICS (Figures 1 and 20)
(V
AVDD
= V
AVDD
= +1.8V to +3.6V, external V
REF
= +1.25V, CLK32K = 32.768kHz (external clock), C
REG
= 10µF, C
CPOUT
= 10µF,
10µF between CF+ and CF-, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Operating Frequency f
SCLK
0 10 MHz
SCLK Cycle Time t
CYC
100 ns
SCLK Pulse-Width High t
CH
40 ns
SCLK Pulse-Width Low t
CL
40 ns
DIN to SCLK Setup t
DS
30 ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to DOUT Valid t
DO
C
L
= 50pF, Figure 2 40 ns
CS Fall to Output Enable t
DV
C
L
= 50pF, Figure 2 48 ns
CS Rise to DOUT Disable t
TR
C
L
= 50pF, Figure 2 48 ns
CS to SCLK Rise Setup t
CSS
20 ns
CS to SCLK Rise Hold t
CSH
0ns
DVDD Monitor Timeout Period t
DSLP
(Note 16) 1.5 s
Wake-Up (WU) Pulse Width t
WU
Minimum pulse width required to detect a
wake-up event
1µs
Shutdown Delay t
DPU
The delay for SHDN to go high after a valid
wake-up event
1µs
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
10 ms
HFCK Turn-On Time t
DFON
If FLLE = 0, the turn-on time for the high-
frequency clock (Note 18)
10 µs
CRDY to INT Delay t
DFI
The delay for CRDY to go low after the
HFCK clock output has been enabled
(Note 19)
7.82 ms
HFCK Disable Delay t
DFOF
The delay after a shutdown command has
asserted and before HFCK is disabled
(Note 20)
1.95 ms
SHDN Assertion Delay t
DPD
(Note 21) 2.93 ms
Note 16: The delay for the sleep voltage monitor output, RESET, to go high after V
DD
rises above the reset threshold. This is largely
driven by the startup of the 32kHz oscillator.
Note 17: It is gated by an AND function with three inputs—the external RESET signal, the internal DV
DD
monitor output, and the
external SHDN signal. The time delay is timed from the internal LOV
DD
going high or the external RESET going high,
whichever happens later. HFCK always starts in the low state.
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT are deasserted.
Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20: t
DFOF
gives the µC time to clean up and go into sleep-override mode properly.
Note 21: t
DPD
is greater than the HFCK delay for the MAX11358B/MAX11359A to clean up before losing power.