Datasheet

7Maxim Integrated
MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis V
HYST
V
OVDD
O 0.15
mV
Input Leakage Current I
IN
V
AIN_
= 0V or V
DD
±0.09 ±1.0
FA
Input Capacitance C
IN
3 pF
DIGITAL OUTPUTS (DOUT, EOC)
Output Voltage Low V
OL
I
SINK
= 200FA
V
OVDD
O 0.15
V
Output Voltage High V
OH
I
SOURCE
= 200FA
V
OVDD
O 0.85
V
Three-State Leakage Current I
L
CS = V
DD
-0.3 ±1.5
FA
Three-State Output Capacitance C
OUT
CS = V
DD
4 pF
POWER REQUIREMENTS
Positive Supply Voltage V
DD
2.35 3.0 3.6 V
Digital I/O Supply Voltage V
OVDD
1.5 3.0 3.6 V
Positive Supply Current I
DD
f
SAMPLE
= 3Msps 5.1 6.5
mAf
SAMPLE
= 0Msps (3Msps devices) 2.5
Full shutdown 0.0013 0.006
Power Dissipation
Normal mode
(external
reference)
V
DD
= 3V,
f
SAMPLE
= 3Msps
15.2
mW
V
DD
= 2.35V,
f
SAMPLE
= 3Msps
10.3
AutoStandby
V
DD
= 3V,
f
SAMPLE
= 3Msps
7.3
V
DD
= 2.35V,
f
SAMPLE
= 3Msps
4.35
Full/
AutoShutdown
V
DD
= 3V 3.9
FW
V
DD
= 2.35V 1.7
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period t
CP
Externally clocked conversion 20.8 ns
SCLK Duty Cycle t
CH
40 60 %
SCLK Fall to DOUT Transition t
DOT
C
LOAD
=
10pF
V
OVDD
= 1.5V to 2.35V 4 16.5
ns
V
OVDD
= 2.35V to 3.6V 4 15
16th SCLK Fall to DOUT Disable t
DOD
C
LOAD
= 10pF, channel ID on 15 ns
14th SCLK Fall to DOUT Disable C
LOAD
= 10pF, channel ID off 16 ns
SCLK Fall to DOUT Enable t
DOE
C
LOAD
= 10pF 14 ns
DIN to SCLK Rise Setup t
DS
4 ns