Datasheet

12Maxim Integrated
MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description (continued)
MAX11329
MAX11331
(16 CHANNEL)
MAX11330
MAX11332
(8 CHANNEL)
NAME FUNCTION
20, 21 20, 21 V
DD
Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
22 22 SCLK Serial Clock Input. Clocks data in and out of the serial interface.
23 23 CS
Active-Low Chip Select Input. When CS is low, the serial interface is enabled.
When CS is high, DOUT is high impedance or three-state.
24 24 DIN
Serial Data Input. DIN data is latched into the serial interface on the rising edge
of SCLK.
25 25 DGND Digital I/O Ground
26 26 OVDD
Digital Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
27 27 DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. When CS is
high, DOUT is high impedance or three-state.
28 28 EOC
End of Conversion Output. Data is valid after EOC is driven low (internal clock mode
only).
— — EP Exposed Pad. Connect EP directly to GND plane for guaranteed performance.