Datasheet
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(MAX1132/MAX1133: AV
DD
= DV
DD
= +5V , f
SCLK
= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps),
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T
A
= 25°C, unless otherwise noted.)
0
0.1 100101
SFDR PLOT
120
MAX1132 toc10
FREQUENCY (kHz)
AMPLITUDE (dB)
100
80
60
40
10
20
30
110
90
70
50
f
SAMPLE
= 200kHz
-110
0.1 100101
THD PLOT
0
MAX1132 toc11
FREQUENCY (kHz)
AMPLITUDE (dB)
-10
-30
-50
-70
-100
-90
-80
-20
-40
-60
f
SAMPLE
= 200kHz
PIN NAME FUNCTION
1 REF
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AV
DD
. Bypass to
AGND with a 2.2µF capacitor when using the internal reference.
2 REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an
external reference, connect REFADJ to AV
DD
to disable the internal bandgap reference.
3 AGND Analog Ground. This is the primary analog ground (Star Ground).
4AV
DD
Analog Supply. 5V ±5%. Bypass AV
DD
to AGND (pin 3) with a 0.1µF capacitor.
5 DGND Digital Ground
6 SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
7 P2 User-Programmable Output 2
8 P1 User-Programmable Output 1
9 P0 User-Programmable Output 0
10 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when CS is high in external clock mode.
11 DOUT
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
12 RST Reset Inp ut. D r i ve RST l ow to p ut the d evi ce i n the p ow er - on d efaul t m od e. S ee the P ow er - O n Reset secti on.
Pin Description