Datasheet

23Maxim Integrated
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 3. ADC Scan Control (continued)
SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION
0 1 0 0 Standard_Ext
Scans channels 0 through N
Clock mode: External clock only
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
0 1 0 1 Upper_Int
Scans channel N through the highest numbered channel. The FIFO
stores X conversion results where:
X = Channel 16–N 16-channel devices
X = Channel 8–N 8-channel devices
Clock mode: Internal clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Can be enabled
0 1 1 0 Upper_Ext
Scans channel N through the highest numbered channel
Clock mode: External clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
0 1 1 1 Custom_Int
Scans preprogrammed channels in ascending order. The FIFO
stores conversion results for this unique channel sequence.
Clock mode: Internal clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: Can be enabled
1 0 0 0 Custom_Ext
Scans preprogrammed channels in ascending order
Clock mode: External clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: No