Datasheet

21Maxim Integrated
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 1. Register Access and Control
Table 2. ADC Mode Control Register
up to 16-channel conversions in ascending order. In this
case, the effective throughput per channel is 1Msps/16
channel or 62.5ksps. The maximum input frequency that
the ADC can resolve (Nyquist Theorem) is 31.25kHz.
If all 16 channels must be measured, with some chan-
nels having greater than 31.25kHz input frequency, the
user must revert back to manual mode requiring con-
stant communication on the serial interface. SampleSet
technology solves this problem. Figure 9 provides a
SampleSet use-model example.
Averaging Mode
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
Scan Modes and Unipolar/Bipolar Setting
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes and only scan even (or odd)
channels (e.g. 0, 2, 4).
REGISTER NAME
REGISTER IDENTIFICATION CODE DIN ≡ DATA INPUTS
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT [10:0]
ADC Mode Control 0 DIN DIN DIN DIN DIN
ADC Configuration 1 0 0 0 0 DIN
Unipolar 1 0 0 0 1 DIN
Bipolar 1 0 0 1 0 DIN
RANGE 1 0 0 1 1 DIN
Custom Scan0 1 0 1 0 0 DIN
Custom Scan1 1 0 1 0 1 DIN
SampleSet 1 0 1 1 0 DIN
Reserved. Do not use. 1 1 1 1 1 DIN
BIT NAME BIT
DEFAULT
STATE
FUNCTION
REG_CNTL 15 0 Set to 0 to select the ADC Mode Control register
SCAN[3:0] 14:11 0001 ADC Scan Control register (Table 3)
CHSEL[3:0] 10:7 0000
Analog Input Channel Select register (Table 4).
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET[1:0] 6:5 00
RESET1 RESET0 FUNCTION
0 0 No reset
0 1 Reset the FIFO only (resets to zero)
1 0 Reset all registers to default settings (includes FIFO)
1 1 Unused