Datasheet

12Maxim Integrated
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description
MAX11321
MAX11322
(4 CHANNEL)
MAX11324
MAX11325
(8 CHANNEL)
MAX11327
MAX11328
(16 CHANNEL)
NAME FUNCTION
1–10, 17, 19 5–10, 17, 19 17, 19 GND Ground
11 11 11 AOP Positive Output from the Multiplexer
12 12 12 AON Negative Output from the Multiplexer
13 13 13 AIP Positive Input to the ADC
14 14 14 AIN Negative Input to the ADC
15 15 — CNVST Active-Low Conversion Start Input
16 16 — REF- External Differential Reference Negative Input
18 18 18 REF+
External Positive Reference Input. Apply a reference voltage at
REF+. Bypass to GND with a 0.47FF capacitor.
20, 21 20, 21 20, 21 V
DD
Power-Supply Input. Bypass to GND with a 10FF in parallel with
a 0.1FF capacitors.
22 22 22 SCLK Serial Clock Input. Clocks data in and out of the serial interface.
23 23 23 CS
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high impedance
or three-state.
24 24 24 DIN
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
25 25 25 DGND Digital I/O Ground
26 26 26 OVDD
Digital Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
27 27 27 DOUT
Serial Data Output. Data is clocked out on the falling edge of
SCLK. When CS is high, DOUT is high impedance or three-
state.
28 28 28 EOC
End of Conversion Output. Data is valid after EOC is driven low
(internal clock mode only).
29–32 — — AIN0–AIN3 Analog Inputs
— — 29–32 , 1–10 AIN0–AIN13 Analog Inputs
— 29–32, 1–4 — AIN0–AIN7 Analog Inputs
— — 15
CNVST/
AIN14
Active-Low Conversion Start Input/Analog Input 14
— — 16 REF-/AIN15 External Differential Reference Negative Input /Analog Input 15
— — — EP
Exposed Pad. Connect EP directly to GND plane for guaranteed
performance.