Datasheet

Electrical Characteristics (continued)
(V
AVDD
= 3.6V, V
AVSS
= 0V, V
DVDD
= 2.0V, V
REFP
= 2.5V, V
REFN
= 0V; f
DATA
= 1000sps, External Clock = 8.192MHz; Continuous
conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI TIMING REQUIREMENTS (See Figures 4–7)
SCLK Frequency f
SCLK
5 MHz
SCLK Clock Period t
CP
200 ns
SCLK Pulse Width High t
CH
Allow 40% duty cycle 80 ns
SCLK Pulse Width Low t
CL
Allow 40% duty cycle 80 ns
CSB Low Setup t
CSS0
CSB low to 1st SCLK rise setup 40 ns
CSB High Setup t
CSS1
Required to prevent a 17th SCLK RE from
being recognized by the device in a free-
running application
40 ns
CSB Hold t
CSH1
SCLK falling edge to CSB rising edge,
CSB hold time
3 ns
CSB Pulse Width t
CSW
Minimum CSB pulse width high 40 ns
DIN Setup t
DS
DIN setup to SCLK rising edge 40 ns
DIN Hold t
DH
DIN hold after SCLK rising edge 0 ns
DOUT Transition t
DOT
DOUT transition valid after SCLK fall 40 ns
DOUT Hold t
DOH
Output hold time remains valid after SCLK
fall
3 ns
DOUT Disable t
DOD
CSB rise to DOUT disable,
C
LOAD
= 20pF
25 ns
CSB Fall to DOUT Valid t
DOE
Default value of DOUT is ‘1’ for minimum
specication, max specication for valid ‘0’
on RDYB
0 40 ns
SCLK Fall to RDYB ‘1’ t
R1
RDYB transitions from ‘0’ to ‘1’ on falling
edge of SCLK after LSB of DATA is shifted
onto DOUT
0 40 ns
RSTB Fall or SYNC Rise to
RDYB ‘1’
t
R2
RDYB transitions from ‘0’ to ‘1’ on falling
edge of RSTB or rising edge of SYNC
after 2 f
CLK
cycles
2 1/f
CLK
Minimum SYNC High Pulse
Width
t
SYNC1
2 1/f
CLK
Minimum RSTB Low Pulse
Width
t
RSTB0
2 1/f
CLK
Note 2: Limits are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3: Noise-free resolution is defined using the peak-to-peak input range and the peak-to-peak noise voltage. The peak-to-peak
noise voltage is defined as the RMS noise voltage times 6.6.
Note 4: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 5: Reference common mode (V
REFP
+ V
REFN
)/2 ≤ (V
AVDD
+ V
AVSS
)/2 +0.1V.
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 9