Datasheet

GPIOs

The MAX11270 provides three general-purpose input/output ports that are programmable through the CTRL4 register.

Set the DIR bits in the CTRL4 register to select the pins to be configured as inputs or outputs. All pins are inputs by

default. When programmed as output, set the DIO bits in the CTRL4 register to set pin state to 0 or 1.

Conversion Synchronization Using SYNC Pin or SYNC_SPI Function

The SYNC pin can be used to synchronize the data conversions to external events. This can be done by either pulling

the SYNC pin high or addressing the SYNC_SPI register in a SPI command byte. There are two methods available in

the device to synchronize conversion results using external signals on the SYNC pin: continuous mode or pulse mode.

Continuous Mode

Continuous synchronization mode is used to detect if the current conversions are synchronized to a continuous syn-

chronization pulse with a period greater than the data rate. This synchronization mode compares the number of device

master clocks between the RDYB assertion to the rising edge of the SYNC pin. The relative edges should stay aligned

within 1 master clock period of the initial SYNC pulse and remain within integer multiples of the data rate. If the rising

edge of the SYNC pin occurs after an integer multiple of the data rate and is greater than plus or minus 1 master clock

from the initial SYNC rising edge then the chip resets the conversion in progress, flushes the digital filter contents and

starts a new conversion. The conversion reset process incurs the full digital filter latency before valid results are available.

See Figure 10 for timing waveform relationships between the chip master clock and the SYNC pin. Due to startup delays,

any SYNC pin assertions before the first RDYB assertion are ignored. The first SYNC pin assertion after a RDYB asser-

tion establishes the relationship between the SYNC pin and the conversion ready, timed in master clock units. This

relationship is defined as n, which constitutes the number of clocks that occur between the assertion of RDYB and the

rising edge of the SYNC pin.

Figure 10. Synchronization Using Continuous Sync Mode Showing Relationship Between SYNC Pin and CLK Pin

SYNC PIN

SYNC1

CNV

5 t

CNV

RDYB

FIRST

CONVERSION

READY

(N + n)

...

CLK

SYNC2

IGNORED

FIRST VALID

SYNC

PART INITIATES A RESET AND RESTARTS CONVERSIONS WHEN THE RELATIONSHIP OF (clk n to clk N+n) IS

MISALIGNED BY MORE THAN ±1 CLK COUNT. IF THE SYNC PIN RISING EDGE IS COINCIDENT WITH CLOCK COUNT

(N+n) THEN THE SOFT_SYNC COMMAND IS IGNORED AND CONVERSIONS CONTINUE UNINTERRUPTED).

MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

www.maximintegrated.com

Maxim Integrated

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