SCLK
RDY
DIN
CS
DOUT
1 8
HIGH-Z HIGH-Z
t
CSS0
t
DS
t
DOE
t
DH
t
DOD
t
CSS1
t
CH
t
CL
t
CP
t
CSH1
‘X’
‘1’ ‘0’ IMPD
CAL
t
CSW
‘X’
SPI COMMAND BYTE
RT2 RT1 RT0
‘X’
RT3
Figure 8. SPI Command Byte Timing Diagram
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated
│
28
