Datasheet

Figure 6. SPI Register Read Timing Diagram
Figure 7. SPI Data Readout Timing Diagram
SCLK
RDY
DIN
CS
DOUT
1 8
HIGH-Z HIGH-Z
t
CSS0
t
DS
t
DOE
t
DH
t
DOD
t
CSS1
t
CH
t
CL
t
CP
t
CSH1
‘X’
‘1’ ‘1’ RS2
RS4 RS3
t
CSW
‘X’
SPI 8b REGISTER READ
RS1 RS0
‘X’
16
‘1’
‘X’
D7 D6 D5 D4 D3 D2 D1 D0
‘X’
‘X’
‘X’ ‘X’ ‘X’ ‘X’
‘X’
‘X’
t
DOT
t
DOH
8b data
SCLK
RDY
DIN
CS
DOUT
MSB
1 8 9
LSB
HIGH-Z
31
39
23
16b data
24b data
32b data
HIGH-Z
t
CSS0
t
DS
t
DOE
t
DH
t
DOT
t
DOH
t
DOD
t
R1
t
CSS1
t
CH
t
CL
t
CP
t
CSH1
t
CSW
‘x’
‘1’ ‘1’ ‘1’ ‘1’
‘1’‘0’ ‘0’ ‘0’
‘x’
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 27