Datasheet

SPI Incomplete Read Command Termination
The SPI interface stays in read mode for as long as CSB
stays low independent of the number of SCLKs issued.
The CSB pin must be toggled high to remove the device
from the bus and reset the internal SPI controller. Any
activity on the DIN pin is ignored while in the register read
mode. The read operation is terminated if the CSB pin
is toggled high before the maximum number of SCLK is
issued.
When reading from DATA registers, the behavior of RDYB
will depend on how many bits are read. If at least 23 bits
are read, the read operation is complete and RDYB resets
to high. If the user reads less than 23 bits, internally the
logic considers the read incomplete, and RDYB stays
low. The user can initiate a new read within the same
conversion cycle and the new 24-bit read must complete
before the next DATA register update.
SPI Timing Characteristics
The SPI timing diagrams illustrating command byte and
register access operations are shown in Figure 4 to
Figure 7. The MAX11270 timing allows for the input data
to be changed by the user at both rising and falling edges
of SCLK. The data read out by the device on SCLK falling
edges can be sampled by the user on subsequent rising
or falling edges.
SCLK
RDYB
DIN
CSB
DOUT
1 8
HIGH-Z HIGH-Z
t
CSS0
t
DS
t
DOE
t
DH
t
DOD
t
CSS1
t
CH
t
CL
t
CP
t
CSH1
‘X’
‘1’ ‘1’ RS2
‘X’ RS3
t
CSW
‘X’
SPI 8b REGISTER WRITE
RS1 RS0
‘X’
16
D7
‘0’
D6 D5 D4 D3 D2 D1 D0 ‘X’
Figure 5. SPI Register Write Timing Diagram
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 26