Datasheet

Table 4. Single-Cycle Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain
with Sinc Filter*
DATA
RATE
(sps)
DIRECT
CONNECT
BUFFER
PGA ENABLED: GAIN SETTING
1 2 4 8 16 32 64 128
LN LP LN LP LN LP LN LP LN LP LN LP LN LP LN LP
50 1.620 1.614 1.655 1.643 0.835 0.833 0.423 0.420 0.219 0.219 0.115 0.120 0.067 0.074 0.046 0.055 0.038 0.048
62.5 1.604 1.652 1.648 1.633 0.850 0.847 0.432 0.433 0.225 0.224 0.118 0.125 0.071 0.079 0.049 0.061 0.043 0.054
100 2.502 2.517 2.524 2.571 1.298 1.285 0.653 0.651 0.344 0.346 0.179 0.186 0.105 0.112 0.068 0.080 0.055 0.070
125 2.479 2.493 2.566 2.580 1.296 1.293 0.666 0.670 0.343 0.347 0.183 0.187 0.105 0.117 0.073 0.088 0.061 0.077
200 3.136 3.232 3.298 3.234 1.655 1.644 0.842 0.834 0.432 0.435 0.232 0.240 0.136 0.150 0.094 0.112 0.078 0.101
250 3.204 3.248 3.297 3.301 1.669 1.649 0.847 0.844 0.439 0.441 0.237 0.248 0.142 0.158 0.101 0.122 0.085 0.111
400 4.961 5.031 5.144 5.151 2.580 2.601 1.311 1.310 0.675 0.684 0.361 0.374 0.206 0.224 0.138 0.165 0.112 0.144
500 4.976 5.076 5.153 5.095 2.603 2.612 1.326 1.331 0.688 0.690 0.368 0.388 0.216 0.238 0.151 0.179 0.127 0.162
800 6.371 6.380 6.556 6.533 3.302 3.298 1.682 1.691 0.869 0.881 0.469 0.487 0.277 0.307 0.194 0.234 0.165 0.212
1000 6.381 6.480 6.597 6.628 3.337 3.344 1.710 1.710 0.883 0.899 0.484 0.509 0.294 0.333 0.214 0.264 0.187 0.240
1600 9.983 10.128 10.317 10.336 5.197 5.227 2.648 2.658 1.367 1.390 0.743 0.771 0.440 0.484 0.306 0.368 0.260 0.333
2000 10.201 10.312 10.479 10.516 5.283 5.299 2.699 2.708 1.403 1.434 0.772 0.809 0.473 0.534 0.350 0.425 0.303 0.389
3200 12.812 12.905 13.183 13.192 6.664 6.649 3.391 3.406 1.764 1.786 0.963 1.006 0.583 0.649 0.419 0.511 0.363 0.466
4000 12.996 13.159 13.416 13.415 6.764 6.795 3.464 3.474 1.815 1.843 1.010 1.071 0.634 0.723 0.478 0.591 0.425 0.544
6400 20.411 20.637 21.067 21.080 10.571 10.598 5.395 5.426 2.816 2.842 1.546 1.617 0.940 1.056 0.686 0.837 0.600 0.758
12800 21.755 21.988 22.412 22.461 11.320 11.330 5.806 5.855 3.051 3.129 1.724 1.847 1.114 1.277 0.860 1.056 0.769 0.975
*V
IN
= 0V. V
AVDD
= 3.6V, V
AVSS
= 0V, V
REF
= 3.6V, T
A
= +25°C, external clock. Data taken with PGA output 150mV from AVDD
and AVSS. This table is not tested and is based on characterization data.
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
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