Datasheet

Input Voltage Range
The ADC input range is programmable for bipolar (-V
REF
to +V
REF
) or unipolar (0 to V
REF
) ranges. The U/B bit in
the CTRL1 register configures the MAX11270 for unipolar
or bipolar transfer functions. See Figure 2.
Noise Performance vs. Data Rate
The MAX11270 offers software-selectable output data
rates in order to optimize data rate and noise. The RATE
bits in the command byte determines the ADC’s output
data rate. The MAX11270 offers zero latency in single-
cycle conversion mode. Set SCYCLE = 0 in the CTRL1
register to run in continuous conversion mode and
SCYCLE = 1 for single-cycle conversion mode.
Single-cycle conversion mode gives an output result with
no data latency for up to 12.8ksps. In continuous conver-
sion mode, the maximum output data rate is 64ksps. In
continuous conversion mode, the output data requires
four additional 24-bit cycles to settle from an input step.
For optimal SNR vs. power, it is recommended to use
different PGA modes. For gain settings 8 and below, use
low-power PGA mode, for gain setting above 8, use low-
noise PGA mode.
AINP
R1
R1
R2
AINN
CAPP
CAPN
C
CAPP/N
(C0G capacitor)
A1
A2
R3
R3
V
AVDD
ANALOG INPUTS PGA OUTPUT
V
AVDD
–
1.3V
V
AVSS
+ 0.3V
V
AVSS
OUTPUT VOLTAGE RANGE = GAIN
x
INPUT VOLTAGE RANGE
INPUT VOLTAGE RANGE
COMMON-MODE
INPUT VOLTAGE
V
AVDD
– 0.3V
≤ V
REF
Figure 1. PGA Structure
Figure 2. Usable Input and Output Common-Mode Range
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 17