Datasheet

Detailed Description
The MAX11270 is an ultra-low power ADC that resolves a
very high dynamic range. This ADC is capable of resolv-
ing microvolt-level changes to the analog input, making it
a good fit for seismic, instrumentation, and ATE applica-
tions. The user can select between programmable gain
amplifier, unity-gain buffer or connect directly to the delta-
sigma sampling network.
The MAX11270 includes a high-accuracy internal oscil-
lator that requires no external components. Data is
output through a serial interface at sample rates up to
12.8ksps with no data latency and 64ksps continuous.
The MAX11270 has a fifth-order digital SINC filter.
The MAX11270 is highly configurable via the internal reg-
isters, which can be accessed via the SPI interface. This
includes PGA gain selection, offset and gain calibration,
and a scalable sample rate to optimize performance.
System Clock
The MAX11270 incorporates a highly stable internal oscil-
lator that provides the system clock. The system clock is
trimmed to 8.192MHz and is divided further down to run
the digital and analog timing.
Voltage Reference Inputs
The MAX11270 provide differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across the REFP and REFN
pins to obtain the differential reference voltage. The
V
REFP
should always be greater than V
REFN
and the
common-mode voltage range is between 0.75V and
V
AVDD
- 0.75V.
Analog Inputs
The MAX11270 measures a pair of differential analog
inputs (AINP, AINN) in buffered, direct connect or PGA.
See the Control 2 Register (Read/Write) section for pro-
gramming and enabling the PGA, buffers, or direct con-
nect. The default configuration is direct connect, with both
PGA and input buffers powered down.
Input Buffers
The input buffer isolates the inputs from the capacitive
load presented by the modulator, allowing for high source-
impedance analog transducers.
Bypass/Direct Connect
The MAX11270 offers the option to bypass both buffers
and PGA and route the analog inputs directly to the modu-
lator. This option lowers the power of the part since both
buffers and PGA are shut off.
Programmable Gain Amplier (PGA)
The integrated PGA provides gain settings from 1x to
128x. See the Control 2 Register (Read/Write) section for
enabling and programming the PGA. The PGA configura-
tion is shown in Figure 1. Direct connection is available
to bypass the PGA enabling direct connection to the
modulator. The PGA’s absolute input voltage range is
CMIRNG and the PGA output voltage range is VOUT
RNG
as specified in the Electrical Characteristics. The PGA
output common-mode voltage is the same as the input
common-mode voltage.
Note that linearity and performance degrade when the
usable input common-mode voltage of the PGA is
exceeded. The usable input common-mode range and
output common-mode range are shown in Figure 2. The
following equations describe the relationship between the
analog inputs and PGA output.
AINP = Positive input to the PGA
AINN = Negative input to the PGA
CAPP = Positive output of PGA
CAPN = Negative output of PGA
V
CM
= Input common mode
GAIN = PGA gain
V
REF
= ADC reference input voltage
V
IN
= V
AINP
- V
AINN
Note: Input voltage range is limited by the reference volt-
age as described by V
IN
≤ ±V
REF
/GAIN
( )
( )
( )
AINP AINN
CM
CAPP CM AINP CM
CAPN CM CM AINN
VV
V
2
V V GAIN V V
V V GAIN V V
−
−−
+
=
=+×
= ×
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 16