Datasheet

PIN NAME FUNCTION
9 AVDD
Analog Positive Supply Voltage. In single-supply mode, V
AVDD
= 2.7V to 3.6V with V
AVSS
= 0V. In
dual-supply mode, AVDD and AVSS can range from ±1.35V to ±1.8V
10, 17 AVSS
Analog Negative Supply Voltage. Connect AVSS to the most negative supply. Connect V
AVSS
= 0V in
single-supply mode. Connect AVSS between -1.8V and 0V for dual-supply mode.
11 AINN
Negative Analog Input. The analog inputs can measure both unipolar and bipolar ranges, depending on
the AVDD and AVSS voltages.
12 AINP
Positive Analog Input. The analog inputs can measure both unipolar and bipolar ranges, depending on
the AVDD and AVSS voltages.
13 REFN
Negative Reference Input. REFN must be less than REFP. REFN voltage must be between AVDD and
AVSS.
14 REFP
Positive Reference Input. REFP must be greater than REFN. REFP voltage must be between AVDD
and AVSS.
15 CAPN PGA Filter Negative Capacitor Output. Connect a 10nF COG capacitor between CAPN and CAPP.
16 CAPP PGA Filter Positive Capacitor Output. Connect a 10nF COG capacitor between CAPN and CAPP.
18 RDYB
Active-Low Data Ready Output or Internal Clock Output. RDYB asserts low when the data is ready.
When in continuous conversion mode, a SYNC or POR event inhibits output of the rst 4 data values to
allow for lter settling when the SINC lter is selected. A SYNC or POR event inhibits output of the rst
63 data values to allow for lter settling when using the FIR lters.
19 CLK
External Clock Input. For external clock mode, set the EXTCLK bit = 1 and provide a digital clock signal
at CLK. The MAX11270 is specied with a clock frequency of 8.192MHz. Other clock frequencies may
be used, but the data rate and digital lter notch frequencies will scale accordingly. This is a digital input
pin and is not internally pulled down. When external clock is disabled drive this pin low.
21 CAPREG
Internal 1.8V Subregulator Reservoir Output. Bypass with a 10µF capacitor to DGND. Minimum
capacitor value required for stability is 220nF.
22 DVDD Digital Supply Voltage. Supply DVDD with 2.0V to 3.6V, with respect to DGND.
23 CSB
Active-Low Chip-Select Input. Set CSB low to access the serial interface. CSB is used for frame
synchronization for communications when SCLK is continuous. Drive CSB high to reset the SPI
interface.
24 SCLK
Serial Clock Input. Apply an external serial clock at SCLK to issue commands or access data from the
MAX11270.
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
www.maximintegrated.com
Maxim Integrated │ 14
Pin Description (continued)