Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 24

General Description

The MAX11270 is a 24-bit delta-sigma ADC that achieves

excellent 130dB SNR while dissipating an ultra-low 10mW.

Sample rates up to 64ksps allow both precision DC and

AC measurements. Integral nonlinearity is guaranteed

to 4ppm maximum. The THD is -122dB. The MAX11270

communicates via an SPI-compatible serial interface and

is available in a small 24-pin TSSOP package.

The MAX11270 offers a 6.5nV/√Hz noise programmable

gain amplifier with gain settings between 1x to 128x.

Optional buffers are also included to provide isolation of

the signal inputs from the switched capacitor sampling

network. This allows the MAX11270 to be used with

high-impedance sources without compromising available

dynamic range.

The MAX11270 operates from a single 2.7V to 3.6V

analog supply, or split ±1.8V analog supplies, allowing

the analog input to be sampled below ground. The digital

supply range is 2.0V to 3.6V, allowing communication with

2.5V, 3V, or 3.3V logic.

Applications

● Scientic Instrumentation

● High-Precision Portable Sensors

● Medical Equipment

● ATE

Features and Benets

● High Resolution for Instrumentation Applications that

Require a Wide Dynamic Range

∙ 130dB SNR at 1.9sps

∙ 112dB SNR at 1000sps

∙ 20.4-Bit Noise-Free Resolution at 1.9sps

∙ 17.4-Bit Noise-Free Resolution at 1000sps

● Longer Battery Life for Portable Applications

∙ 2.4mA Operating Mode Current

∙ 4.4mA PGA Low-Noise Mode Current

∙ 1μA Sleep Current

● High Accuracy for DC Measurements

∙ 1ppm INL (typ), 4ppm (max)

● Single or Split Analog Supplies Provide Input Voltage

Range Flexibility

∙ 2.7V to 3.6V (Single Supply) or

±1.8V (Split Supplies)

● Flexible High-Performance Filter Architecture

Simplifies Design

∙ Programmable SINC Filter

● Enables System Integration

∙ Low-Noise PGA with Gains of 1, 2, 4, 8, 16, 32,

64, 128

∙ Signal Buffer Optional

∙ 3 General-Purpose I/Os

● Enables Integrated Part and System Calibration for

Gain and Offset

● Robust 24-Pin TSSOP Packaging

19-7048; Rev 0; 8/14

Ordering Information and Functional Diagram appear at

end of data sheet.

MAX11270

µC

REF

10nF

C0G

AINN

GPIO3 GPI01

AINP

10nF

REFN REFP

1µF

AVDD

2.7V TO 3.6V

.0V TO 3.6V

CAPP CAPN

10nF

C0G

RDY

DOUT

SCLK

SYNC

DVDD

RST

CSB

1µF

CAPREG

DGNDAVSSAVSS

GPI02

DIN

1µF

0603

X7R

Typical Application Circuit

MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

EVALUATION KIT AVAILABLE

Summary of content (46 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA General Description Features and Benefits The MAX11270 is a 24-bit delta-sigma ADC that achieves excellent 130dB SNR while dissipating an ultra-low 10mW. Sample rates up to 64ksps allow both precision DC and AC measurements. Integral nonlinearity is guaranteed to 4ppm maximum. The THD is -122dB.
PAGE 2
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features and Benefits . . . . . . . . . . . . . . . . . . .
PAGE 3
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA TABLE OF CONTENTS (continued) Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Status Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA LIST OF FIGURES Figure 1. PGA Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 2. Usable Input and Output Common-Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3a. SINC Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA LIST OF TABLES Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2. Continuous Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . 19 Table 3. Single-Cycle Mode SNR (dB) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4.
PAGE 6
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Absolute Maximum Ratings AVDD to AVSS......................................................-0.3V to +3.9V DVDD to DGND.....................................................-0.3V to +3.9V DVDD to AVSS......................................................-0.3V to +3.9V AVSS to DGND...................................................-1.95V to +0.3V Analog Inputs (AINP, AINM, REFP, REFN, CAPP, CAPN) to AVSS............ -0.
PAGE 7
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Electrical Characteristics (continued) (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 8
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Electrical Characteristics (continued) (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 9
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Electrical Characteristics (continued) (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 10
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Typical Operating Characteristics (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) ACTIVE CURRENT vs. TEMPERATURE 3.50 BYPASS MODE 1000.00 1.50 1.00 0.
PAGE 11
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Typical Operating Characteristics (continued) (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) 400 0.8 350 0.
PAGE 12
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Typical Operating Characteristics (continued) (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) OUTPUT SPECTRUM SHORTED INPUTS 0 -40 SNR vs.
PAGE 13
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Pin Configuration TOP VIEW + 24 SCLK 2 23 CSB DGND 3 22 DVDD SYNC 4 21 CAPREG RSTB 5 20 DGND GPIO3 6 19 CLK RDYB DIN 1 DOUT MAX11270 GPIO2 7 18 GPIO1 8 17 AVSS AVDD 9 16 CAPP AVSS 10 15 CAPN AINN 11 14 REFP AINP 12 13 REFN TSSOP Pin Description PIN NAME 1 DIN 2 DOUT Serial Data Output or Real-Time Modulator MB0 Output.
PAGE 14
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Pin Description (continued) PIN NAME FUNCTION 9 AVDD Analog Positive Supply Voltage. In single-supply mode, VAVDD = 2.7V to 3.6V with VAVSS = 0V. In dual-supply mode, AVDD and AVSS can range from ±1.35V to ±1.8V 10, 17 AVSS Analog Negative Supply Voltage. Connect AVSS to the most negative supply. Connect VAVSS = 0V in single-supply mode. Connect AVSS between -1.8V and 0V for dual-supply mode.
PAGE 15
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Functional Diagram REFP DVDD REFN AVDD GPIO1 GPIO2 1.8V REGULATOR GPIO3 MAX11270 CAPREG RST SYNC BUFFER RDY AIN+ DIN CAPP PGA CAPN SIGMA DELTA MODULATOR SERIAL INTERFACE SINC FILTER AIN- SCLK DOUT CSB BUFFER CLOCK GENERATOR TIMING AVSS www.maximintegrated.
PAGE 16
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Detailed Description The MAX11270 is an ultra-low power ADC that resolves a very high dynamic range. This ADC is capable of resolving microvolt-level changes to the analog input, making it a good fit for seismic, instrumentation, and ATE applications. The user can select between programmable gain amplifier, unity-gain buffer or connect directly to the deltasigma sampling network.
PAGE 17
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Input Voltage Range AINP A1 R3 CAPP Noise Performance vs. Data Rate R1 R2 AINN CCAPP/N (C0G capacitor) R1 A2 The ADC input range is programmable for bipolar (-VREF to +VREF) or unipolar (0 to VREF) ranges. The U/B bit in the CTRL1 register configures the MAX11270 for unipolar or bipolar transfer functions. See Figure 2. R3 CAPN Figure 1.
PAGE 18
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter* DIRECT CONNECT BUFFER PGA ENABLED: GAIN SETTING DATA RATE (sps) LN LP LN LP LN LP LN LP LN LP LN LP LN LP LN LP 1.9 129.8 130.2 128.8 128.7 130.0 129.5 129.8 129.8 130.0 130.0 129.7 129.7 130.0 129.5 128.7 127.6 126.1 124.0 3.9 129.8 129.9 128.6 128.5 130.1 129.9 130.0 129.7 129.9 129.7 129.4 129.
PAGE 19
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 2. Continuous Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* DIRECT CONNECT BUFFER PGA ENABLED: GAIN SETTING DATA RATE (sps) LN LP LN LP LN LP LN LP LN LP LN LP LN LP LN LP 1.9 0.825 0.805 0.837 0.838 0.451 0.475 0.220 0.217 0.109 0.110 0.058 0.057 0.029 0.031 0.017 0.019 0.011 0.020 3.9 0.824 0.833 0.857 0.865 0.446 0.455 0.215 0.222 0.111 0.
PAGE 20
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 3. Single-Cycle Mode SNR (dB) vs. Data Rate and PGA Gain with Sinc Filter* DIRECT CONNECT BUFFER PGA ENABLED: GAIN SETTING LN LP LN LP LN LP LN LP LN LP LN LP LN LP LN LP 123.9 123.6 119.0 119.0 121.9 121.9 123.3 123.3 123.2 123.2 123.0 122.7 122.0 121.1 119.1 117.6 114.1 112.1 124.0 123.4 119.0 119.0 121.7 121.7 123.1 123.1 123.0 123.0 122.8 122.3 121.5 120.5 118.7 116.
PAGE 21
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 4. Single-Cycle Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* DIRECT CONNECT BUFFER PGA ENABLED: GAIN SETTING DATA RATE (sps) LN LP LN LP LN LP LN LP LN LP LN LP LN LP LN LP 50 1.620 1.614 1.655 1.643 0.835 0.833 0.423 0.420 0.219 0.219 0.115 0.120 0.067 0.074 0.046 0.055 0.038 0.048 62.5 1.604 1.652 1.648 1.633 0.850 0.847 0.432 0.433 0.
PAGE 22
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Power-On Reset The MAX11270 contains power-on reset (POR) supply monitoring circuitry on both the digital supply (DVDD) and the positive analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. The digital POR trigger threshold is typically 1.2V with respect to VDGND and has 100mV of hysteresis. The analog POR trigger threshold is typically 1.
PAGE 23
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 5.
PAGE 24
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Digital Filters is used to reset the SPI interface. When CSB is low, data is clocked into the device from DIN on the rising edge of SCLK. Data is clocked out of DOUT on the falling edge of SCLK. When CSB is high, SCLK and DIN are ignored and DOUT is high impedance allowing DOUT to be shared with other devices.
PAGE 25
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA DOUT (Serial Data Output) SPI Incomplete Write Command Termination The DOUT pin is actively driven when CSB is low and high impedance when CSB is high. Data are shifted out on DOUT on the falling edge of SCLK. In case of register writes, the register values get updated every 8th clock cycle with a byte of data starting from the MSB.
PAGE 26
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA SPI Incomplete Read Command Termination SPI Timing Characteristics The SPI interface stays in read mode for as long as CSB stays low independent of the number of SCLKs issued. The CSB pin must be toggled high to remove the device from the bus and reset the internal SPI controller. Any activity on the DIN pin is ignored while in the register read mode.
PAGE 27
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA SPI 8b REGISTER READ ‘X’ RDY tCSW tCSS0 tCSH1 CS tCH SCLK tCL tCP 1 ‘1’ ‘X’ 16 8 tDS DIN tCSS1 ‘1’ RS4 RS3 RS2 RS1 RS0 ‘1’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ tDOT tDOE DOUT 8b data tDH HIGH-Z ‘X’ D7 ‘X’ ‘X’ ‘X’ ‘X’ tDOH D6 D5 D4 D3 tDOD D2 D1 HIGH-Z D0 Figure 6.
PAGE 28
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA SPI COMMAND BYTE RDY ‘X’ tCSW tCSS0 tCSH1 CS tCH SCLK tCL 1 tCP 8 tDS DIN ‘X’ ‘1’ ‘0’ tDH CAL IMPD RT3 HIGH-Z RT2 RT1 RT0 tDOD tDOE DOUT tCSS1 ‘X’ HIGH-Z Figure 8. SPI Command Byte Timing Diagram www.maximintegrated.
PAGE 29
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Modes and Registers The MAX11270 interface operates in two modes, conversion mode or register access mode, which is selected by the command byte. Every SPI transaction to the MAX11270 starts with a command byte. The command byte begins with a START bit (B7), which must be set to 1. The next bit is the MODE bit (B6), which selects between conversion mode or register access mode.
PAGE 30
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Register Map Register Address Map There are 14 registers that can be accessed in the MAX11270. The majority of registers can be both written to and read from, but the STAT and DATA registers are read only. The RAM and SYNC are not physical registers, but addresses to enable special operating modes. Table 8.
PAGE 31
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Status Register (Read Only) The 16-bit status register is a read-only register that indicates the following: power-down status, if the modulator was reset or overloaded, the data rate, overrange condition, when a measurement is in progress and when a measurement is complete.
PAGE 32
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 9. Programmable Conversion Rates CONTINUOUS DATA RATE, SCYCLE = 0 SINC FILTER (sps) SCYCLE = 1 SINGLE-CYCLE CONTINUOUS DATA RATE (sps) 0000 1.9 50 0001 3.9 62.5 0010 7.8 100 RATE[3:0] 0011 15.6 125 0100 31.2 200 0101 62.
PAGE 33
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Control Registers These are registers reserved for configuring the MAX11270. Control 1 Register (Read/Write) The CTRL1 register is an 8-bit read/write register. The byte written to the CTRL1 register determines the clock setting, synchronization mode, power-down or reset state, input range is unipolar or bipolar, data output is two’s complement or offset binary, and conversion mode is in single cycle or continuous.
PAGE 34
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Control 2 Register (Read/Write) The CTRL2 register is an 8-bit read/write register. The byte written to the CTRL2 register determines the digital and analog gain settings, and whether the buffers or PGA is enabled.
PAGE 35
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Control 3 Register (Read/Write) The CTRL3 register is an 8-bit read/write register. The byte written to the CTRL3 register determines the operation of the modulator output.
PAGE 36
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Control 5 Register (Read/Write) The CTRL5 register is an 8-bit read/write register. The byte written to the CTRL5 register determines the MAX11270’s reset, data overflow, and calibration modes. BIT B07 B06 B05 B04 B03 B02 B01 B00 BIT NAME CAL1 CAL0 — — NOSYSG NOSYSO NOSCG NOSCO DEFAULT 0 0 0 0 1 1 0 0 BIT DEFAULT 00 LABEL 0 FUNCTION NOSCO No self-calibration offset bit.
PAGE 37
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Table 10.
PAGE 38
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Request a system full-scale calibration by setting the CAL bit to 1 and the CTRL5:CAL[1:0] = 10 and connect a system full-scale signal level to the input pins. The system full-scale calibration requires 100ms to complete, and the SGC register contains values that correct for the chip full-scale value.
PAGE 39
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA SPI Self-Cal Offset Calibration Register (SCOC_SPI) The Self-Cal Offset register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. The format is always in two’s complement format. This register temporarily holds the self-cal offset calibration value from the user. This value gets copied into the SCOC_ADC register.
PAGE 40
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA RAW RESULT SPI BLOCK CAL BLOCK NOSCO=0 F T SCOC SUBTRACT SCOC_ADC 24 NOSCG=0 F T SCGC MULTIPLY SCGC_ADC 24 NOSYSO=0 F T SOC SUBTRACT SOC_ADC 24 NOSYSG=0 F T SGC MULTIPLY SGC_ADC 24 DATA FINAL RESULT F UNIPOLAR T STATUS REG x2 LIMITER Figure 9. Calibration Flow Diagram www.maximintegrated.
PAGE 41
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA GPIOs The MAX11270 provides three general-purpose input/output ports that are programmable through the CTRL4 register. Set the DIR bits in the CTRL4 register to select the pins to be configured as inputs or outputs. All pins are inputs by default. When programmed as output, set the DIO bits in the CTRL4 register to set pin state to 0 or 1.
PAGE 42
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA TOP VIEW DIN tSYNC2 tSYNC1 SYNC PIN 5 tCNV tCNV SINC FILTER, RDYB ... 1ST CONVERSION READY AFTER PULSE SYNCHRONIZATION ...
PAGE 43
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA DOUT/MB0 GPIO1/MB1 In MODBIT mode, the DOUT/MB0 outputs the real-time modulator data (MB0). When the ENMSYNC bit = 0, DOUT/ MB0 outputs the first MSYNC pulse and shifts out the even bits of the modulator data (bit 4, bit 2, and bit 0). The first SYNC pulse (indicating valid modulator data) will be shifted out on the positive clock edge (referred to as clock edge 1) for initial synchronization.
PAGE 44
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA WRITE TO CTRL3[5:4]=01 OR 11 WRITE TO CTRL3[5:4]=00 OR 10 ISSUE A CONVERSION COMMAND ISSUE A CONVERSION COMMAND MCLK EN_MODBITS (INTERNAL SIGNAL) 1 2 3 4 1 2 3 4 RDYB_ICLK SYNC1 GPIO3_MSYNC (SYNC PULSES OUT) DOUT_MB0 GPIO1_MB1 SYNC2 CASE1: ENMSYNC (CTRL3[5]=1) 0 MDATA4 MDATA2 MDATA0 0 MDATA4 MDATA2 MDATA0 0 0 MDATA3 MDATA1 0 0 MDATA3 MDATA1 0 0 CASE2: ENMSYNC (CTRL3[5]=0) OVRRNG=0 DOUT_MB0
PAGE 45
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA Ordering Information Package Information PART TEMP RANGE PIN-PACKAGE MAX11270EUG+ -40°C to +85°C 24 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. Chip Information PROCESS: BiCMOS www.maximintegrated.com For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 46
MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta Sigma ADC with Integrated PGA Revision History REVISION NUMBER REVISION DATE 0 8/14 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.