Datasheet

15Maxim Integrated
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11209/MAX11211
Figure 7. SPI Register Access Read
Table 5. Command Byte (MODE = 0)
Table 6. Command Byte (MODE = 1)
Note: The START bit is used to synchronize the data from the host device. The START bit is always 1.
Command Byte
Communication between the user and the device is con-
ducted through SPI using a command byte. The com-
mand byte consists of two modes differentiated as com-
mand modes and data modes. Command modes and
data modes are further differentiated by decoding the
remaining bits in the command byte. The mode selected
is determined by the MODE bit. If the MODE bit is 0, then
the user is requesting either a conversion, calibration, or
power-down; see Table 5. If the MODE bit is 1, then the
user is selecting a data command and can either read
from or write to a register; see Table 6.
The Status register (STAT1) is a read-only register and
provides general chip operational status to the user. If
the user attempts to calibrate the system and overranges
the internal signal scaling, then a gain overrange condi-
tion is flagged with the SYSOR bit. The last data rate
programmed for the ADC is available in the RATE bits.
If the input signal has exceeded positive or negative full
scale, this condition is flagged with the OR and UR bits.
If the modulator is busy converting, then the MSTAT bit
is set. If a conversion result is ready for readout, the RDY
bit is set; see Table 11.
The Control 1 register (CTRL1) is a read/write register,
and the bits determine the internal oscillator frequency,
unipolar or bipolar input range, selection of an internal or
external clock, enabling or disabling the reference and
input signal buffers, the output data format (offset binary
or two’s complement), and single-cycle or continuous
conversion mode. See Table 12.
The Control 2 register (CTRL2) is a read/write register,
and the bits configure the GPIOs as inputs or outputs
and their values. See Table 13.
The Control 3 register (CTRL3) is a read/write register,
and the bits determine the MAX11209 programmable
gain setting and the calibration register settings for both
the MAX11209 and MAX11211. See Table 14.
The Data register (DATA) is a read-only register. Data is
output from RDY/DOUT on the next 24 SCLK cycles once
CS is forced low. The data bits transition on the falling
edge of SCLK. Data is output MSB first, and is offset
binary or two’s complement, depending on the setting
of the FORMAT bit in the CTRL1 register. See Table 15.
The System Offset Calibration register (SOC) is a read/
write register, and the bits contain the digital value that
corrects the data for system zero scale. See Table 17.
The System Gain Calibration register (SGC) is a read/
write register, and the bits contain the digital value that
corrects the data for system full scale. See Table 18.
The Self-Cal Offset Calibration register (SCOC) is a read/
write register, and the bits contain the value that corrects
the data for chip zero scale. See Table 19.
The Self-Cal Gain Calibration register (SCGC) is a read/
write register, and the bits contain the value that corrects
the data for chip full scale. See Table 20.
t
DOE
HIGH-Z
HIGH-Z
SCLK
X
1
11X RS3 RS2 RS1 RS0
W/R XX X XXXXX
D6D7 D5 D4 D3 D2 D1 D0
1689
DIN
t
CP
t
DOD
t
DOT
t
DO1
t
DOH
CS
RDY/DOUT
t
CSS0
t
DS
t
CSS1
t
CL
t
CH
t
DH
BIT B7 B6 B5 B4 B3 B2 B1 B0
BIT NAME
START = 1 MODE = 0 CAL1 CAL0 IMPD RATE2 RATE1 RATE0
BIT B7 B6 B5 B4 B3 B2 B1 B0
BIT NAME
START = 1 MODE = 1 0 RS3 RS2 RS1 RS0
W/R