Datasheet
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
8 _______________________________________________________________________________________
V
DD
I/O
SCK (SK)
MISO (SI)
GND
DOUT
SCLK
CNVST
GND
V
DD
0.1μF
1μF
CH0
REF*
* MAX1118 ONLY
1μF
ANALOG
INPUTS
MAX1117
MAX1118
MAX1119
CPU
V
DD
CH1
Figure 3. Typical Operating Circuit
GND
C
HOLD
CAPACITIVE DAC
COMPARATOR
16pF
R
IN
6.5kΩ
AUTOZERO
RAIL
TRACK
HOLD
CH0
CH1
Figure 4. Equivalent Input Circuit
Detailed Description
The MAX1117/MAX1118/MAX1119 ADCs use a suc-
cessive-approximation conversion technique and input
T/H circuitry to convert an analog signal to an 8-bit digi-
tal output. The SPI/QSPI/MICROWIRE compatible inter-
face directly connects to microprocessors (µPs) without
additional circuity (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in Figure
4’s equivalent-input circuit and is composed of the T/H,
the input multiplexer, the input comparator, the
switched capacitor DAC, and the auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog
inputs (CH0, CH1) are connected to the holding capac-
itor (C
HOLD
). Once the acquisition has completed, the
T/H switch opens and C
HOLD
is connected to GND,
retaining the charge on C
HOLD
as a sample of the sig-
nal at the analog input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance <1.5kΩ is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs will also improve the accu-
racy of an input sample.
Conversion Process
The MAX1117/MAX1118/MAX1119 conversion process
is internally timed. The total acquisition and conversion
process takes <7.5µs. Once an input sample has been
acquired, the comparator’s negative input is then con-
V
DD
3kΩ
C
LOAD
GND
DOUT
C
LOAD
GND
3kΩ
DOUT
a) V
OL
TO V
OH
b) HIGH-Z to V
OL
AND V
OH
to V
OL
V
DD
3kΩ
C
LOAD
GND
DOUT
C
LOAD
GND
3kΩ
DOUT
a) V
OH
TO HIGH-Z b) V
OL
TO HIGH-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time