Datasheet
Maxim Integrated
│
5
MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
www.maximintegrated.com
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz or 250kHz, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25NC.) (Note 2)
Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C
and +85°C. Limits below +25°C are guaranteed by design and device characterization. Typical values are not guaranteed.
Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.
Note 4: See the Definitions section.
Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the V
DD
supply voltage.
Note 6: 10kHz sine wave input, -0.1dB below full scale.
Note 7: See Table 4 for definition of the reference modes.
Note 8: f
IN1
~ 9.4kHz, f
IN2
~ 10.7kHz, Each tone at -6.1dB below full scale.
Note 9: C
LOAD
= 65pF on DOUT.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING (Note 9)
Time Between Conversions t
CYC
MAX11166 2 100000 µs
MAX11167 4 100000 µs
Conversion Time t
CONV
CNVST rising to
data available
MAX11166 1.35 1.5
µs
MAX11167 2.7 3.0
Acquisition Time t
ACQ
t
ACQ
= t
CYC
- t
CONV
MAX11166 0.5
µs
MAX11167 1
CNVST Pulse Width t
CNVPW
CS mode
5 ns
SCLK Period (CS Mode)
t
SCLK
V
OVDD
> 4.5V 14
nsV
OVDD
> 2.7V 20
V
OVDD
> 2.3V 26
SCLK Period (Daisy-Chain Mode) t
SCLK
V
OVDD
> 4.5V 16
nsV
OVDD
> 2.7V 24
V
OVDD
> 2.3V 30
SCLK Low Time t
SCLKL
5 ns
SCLK High Time t
SCLKH
5 ns
SCLK Falling Edge to Data Valid
Delay
t
DDO
V
OVDD
> 4.5V 12
nsV
OVDD
> 2.7V 18
V
OVDD
> 2.3V 23
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
t
EN
V
OVDD
> 2.7V 14
ns
V
OVDD
< 2.7V
17
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
t
DIS
CS Mode
20 ns
DIN Valid Setup Time from SCLK
Falling Edge
t
SDINSCK
V
OVDD
> 4.5V 3
nsV
OVDD
> 2.7V 5
V
OVDD
> 2.3V 6
DIN Valid Hold Time from SCLK
Falling Edge
t
HDINSCK
0 ns
SCLK Valid Setup Time to
CNVST Falling Edge
t
SSCKCNF
3 ns
SCLK Valid Hold Time to CNVST
Falling Edge
t
HSCKCNF
6 ns