Datasheet

Maxim Integrated │ 28
MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
www.maximintegrated.com
Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing
Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated, it
continues to completion irrespective of the state of CNVST.
When a conversion is complete, the busy indica tor is pre-
sented onto each DOUT and the MAX11166/ MAX11167
return to the acquisition phase. The busy indicator for the
last ADC in the chain can be connected to an interrupt input
on the digital host. The digital host should insert a 50ns
delay from the receipt of this interrupt before reading out
data from all ADCs to ensure that all devices in the chain
have completed conversion.
The conversion data is stored within an internal shift reg-
ister. To read these bits out, CNVST is brought low and
each bit is shifted out on subsequent SCLK falling edge.
The DIN input of each ADC in the chain is used to transfer
conversion data from the previous ADC into the internal
shift register of the next ADC, thus allowing for data to be
clocked through the multichip chain on each SCLK falling
edge. The total of number of falling SCLKs needed to read
back all data from N ADCs is 16 × N + 1 edges, the one
additional SCLK falling edge required to clock out the busy
mode bit from the host side ADC.
MAX11166
MAX11167
MAX11166
MAX11167
CLK
DATA IN
DIGITAL HOST
CONFIG
CONVERT
SCLK
DEVICE B
CNVST
SCLK
DEVICE A
CNVST
DOUT
D
B
DINDIN
DOUT
D
A
SCLK 1231516
CNVST
t
CONV
CONVERSIONACQUISITION ACQUISITION
t
ACQ
t
SCLK
t
SCLKL
t
SCLKH
t
DDO
30 31 3217 18
DOUT
B
D
B
15 D
B
14 D
B
13 D
B
1D
B
0D
A
15 D
A
14 D
A
1D
A
0
t
CNVPW
DIN
t
CYC
14
t
HSCKCNF
t
SSCKCNF