Datasheet

Maxim Integrated │ 26
MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
www.maximintegrated.com
Multichannel CS Conguration,
Asynchronous or Simultaneous Sampling
The multichannel CS configuration is generally used when
multiple MAX11166/MAX11167 ADCs are connected to an
SPI-compatible digital host. Figure 10 shows the connec-
tion diagram example using two MAX11166/MAX11167
devices. Figure 11 shows the corresponding timing.
Asynchronous or simultaneous sampling is possible by
controlling the CS1 and CS2 edges. In Figure 10, the DOUT
bus is shared with the digital host limiting the throughput
rate. However, maximum throughput is possible if the host
accommodates each ADC’s DOUT pin independently.
A rising edge on CNVST completes the acquisition,
initiates the conversion and forces DOUT to high
impedance. The conversion continues to completion
irrespective of the state of CNVST allowing CNVST
to be used as a select line for other devices on the
board. However, CNVST must be returned high before
the minimum conversion time for proper operation so
that another conversion is not initiated with insufficient
acquisition time and data correctly read out of the
device.
When the conversion is complete, the MAX11166/
MAX11167 enter the acquisition phase. Each ADC result
can be read by bringing its CNVST input low, which conse-
quently outputs the MSB onto DOUT. The remaining data
bits are then clocked by subsequent SCLK falling edges.
For each device, its DOUT will return to a high-impedance
state after the 16
th
SCLK falling edge or when CNVST
goes high. This control allows multiple devices to share
the same DOUT bus.
Daisy-Chain, No-Busy Indicator Mode
Figure 10. Multichannel CS Configuration Diagram
MAX11166
MAX11167
MAX11166
MAX11167
CLK
DATA IN
DIGITAL HOST
CS2
CS1
CONFIG
DOUT
SCLK
DEVICE B
CNVST
SCLK
DEVICE A
CNVST
DIN
DOUT
DIN