Datasheet

Maxim Integrated │ 25
MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
www.maximintegrated.com
Figure 9. CS With Busy Indicator Mode Timing
When the conversion is complete, DOUT transitions from
high impedance to a low logic level, signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11166/MAX11167 then enter the
acquisition phase. The data bits are then clocked out,
MSB first, by subsequent SCLK falling edges. DOUT
returns to high impedance after the 17th SCLK falling
edge or when CNVST goes high, and is then pulled to
OVDD through the external pullup resistor.
t
CNVPW
D14D15BUSY BIT
DOUT
SCLK
ACQUISITION ACQUISITIONCONVERSION
DIN
CNVST
D13 D1 D0
1234 15 16 17
t
CONV
t
ACQ
t
CYC
t
SCLKL
t
SCLK
t
DDO
t
SCLKH
t
DIS
t
HSCKCNF
t
SSCKCNF