Datasheet

Maxim Integrated │ 24
MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
www.maximintegrated.com
Figure 7. CS No Busy Indicator Mode Timing
Figure 8. CS With Busy Indicator Mode Connection Diagram
CS with Busy Indicator Mode
The CS with busy indicator mode is shown in Figure 8
where a single ADC is connected to a SPI-compatible
digital host with interrupt input. The corresponding timing
is given in Figure 9.
A rising edge on CNVST completes the acquisition, initi-
ates the conversion and forces DOUT to high impedance.
The conversion continues to completion irrespective of
the state of CNVST allowing CNVST to be used as a
select line for other devices on the board.
t
CONV
t
ACQ
DIN
ACQUISITION
SCLK
DOUT
CONVERSION ACQUISITION
12 3141516
t
DDO
t
EN
t
SCLKH
t
SCLKL
t
HSCKCNF
t
SSCKCNF
D15 D14 D13 D1 D0
CNVST
t
CNVPW
t
CYC
t
SCLK
t
DIS
CLK
DATA IN
IRQ
OVDD
10kΩ
DIGITAL HOST
CONVERT
CONFIG
DOUT
SCLK
CNVST
DIN
MAX11166
MAX11167