Datasheet

8Maxim Integrated
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
Note 2: Limits are 100% production tested at T
A
= +25NC. Limits over the operating temperature range are guaranteed by design.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(D
OUT
) with V
DD
= 2.35V to 3.6V and V
REF+
= 2.35V.
Note 7:
Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 1.91Fs + N x 16 x T
OSC_MAX
T
OSC_MAX
= 29.4ns, T
OSC_TYP
= 25ns.
Note 9:
The operational input voltage range for each individual input of a differentially configured pair is from V
DD
to GND. The
operational input voltage difference is from -V
REF+
/2 to +V
REF+
/2 or -V
REF+
to +V
REF+
.
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period t
CP
Externally clocked conversion 20.8 ns
SCLK Duty Cycle t
CH
40 60 %
SCLK Fall to DOUT Transition t
DOT
C
LOAD
=
10pF
V
OVDD
= 1.5V to 2.35V 4 16.5
ns
V
OVDD
= 2.35V to 3.6V 4 15
16th SCLK Fall to DOUT Disable t
DOD
C
LOAD
= 10pF, channel ID on 15 ns
14th SCLK Fall to DOUT Disable C
LOAD
= 10pF, channel ID off 16 ns
SCLK Fall to DOUT Enable t
DOE
C
LOAD
= 10pF 14 ns
DIN to SCLK Rise Setup t
DS
4 ns
SCLK Rise to DIN Hold t
DH
1 ns
CS Fall to SCLK Fall Setup
t
CSS
4 ns
SCLK Fall to CS Fall Hold
t
CSH
1 ns
CNVST Pulse Width
t
CSW
See Figure 6 5 ns
CS or CNVST Rise to EOC Low
(Note 7)
t
CNV_INT
See Figure 7, f
SAMPLE
= 3Msps 2.1 2.4
Fs
CS Pulse Width
t
CSBW
5 ns