Datasheet

MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
8Maxim Integrated
ELECTRICAL CHARACTERISTICS (MAX11120/MAX11123/MAX11126)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 1Msps, f
SCLK
= 16MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
ELECTRICAL CHARACTERISTICS (MAX11121/MAX11124/MAX11127)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 1Msps, f
SCLK
= 16MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period t
CP Externally clocked conversion 62.4 ns
SCLK Duty Cycle t
CH 40 60 %
SCLK Fall to DOUT Transition t
DOT
CLOAD =
10pF
V
OVDD = 1.5V to 2.35V 4 16.5
ns
V
OVDD = 2.35V to 3.6V 4 15
16th SCLK Fall to DOUT Disable t
DOD CLOAD = 10pF, channel ID on 15 ns
14th SCLK Fall to DOUT Disable C
LOAD = 10pF, channel ID off 16 ns
SCLK Fall to DOUT Enable t
DOE CLOAD = 10pF 14 ns
DIN to SCLK Rise Setup t
DS 4 ns
SCLK Rise to DIN Hold t
DH 1 ns
CS Fall to SCLK Fall Setup t
CSS 4 ns
SCLK Fall to CS Fall Hold t
CSH 1 ns
CNVST Pulse Width t
CSW See Figure 6 5 ns
CS or CNVST Rise to EOC Low
(Note 8)
t
CNV_INT See Figure 7, fSAMPLE = 1Msps 5.3 6.2 Fs
CS Pulse Width t
CSBW 5 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Notes 3 and 4)
Resolution RES 8 bit 8 Bits
Integral Nonlinearity INL ±0.02 ±0.15 LSB
Differential Nonlinearity DNL No missing codes ±0.02 ±0.15 LSB
Offset Error 0.5 ±0.7 LSB
Gain Error (Note 5) -0.03 ±0.3 LSB
Offset Error Temperature
Coefficient
OE
TC
±2
ppm/NC
Gain Temperature Coefficient GE
TC
±0.8
ppm/NC
Channel-to-Channel Offset
Matching
±0.5 LSB
Line Rejection PSR (Note 6) +0.03 ±0.1 LSB/V