Datasheet

MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Figures 8 and 9)
(V
DD
= 2.7V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: See
Typical Operating Characteristics.
Note 3: V
REFIN
= 2.048V, offset nulled.
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for the analog inputs is from AGND to V
DD
.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10: Measured as
| V
FS
(2.7V) - V
FS
(3.6V) |.
Note 11: 1µF at REFOUT; internal reference settling to 0.5 LSB.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Track/Hold Acquisition Time t
ACQ
1µs
DIN to SCLK Setup t
DS
100 ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to Output Data Valid t
DO
Figure 1, C
LOAD
= 100pF 20 200 ns
CS Fall to Output Enable t
DV
Figure 1, C
LOAD
= 100pF 240 ns
CS Rise to Output Disable t
TR
Figure 2, C
LOAD
= 100pF 240 ns
CS to S C LK Ri se S etup t
CSS
100 ns
CS to SCLK Rise Hold t
CSH
0ns
SCLK Pulse Width High t
CH
200 ns
SCLK Pulse Width Low t
CL
200 ns
SCLK Fall to SSTRB t
SSTRB
C
LOAD
= 100pF 240 ns
CS Fall to SSTRB Output Enable
(Note 6)
t
SDV
Figure 1, external clock mode only,
C
LOAD
= 100pF
240 ns
CS Rise to SSTRB output
Disable (Note 6)
t
STR
Figure 2, external clock mode only,
C
LOAD
= 100pF
240 ns
SSTRB Rise to SCLK Rise
(Note 6)
t
SCK
Figure 11, internal clock mode only 0 ns
External reference 20 µs
Wake-Up Time
t
WAKE
Internal reference (Note 11) 12 ms