Datasheet

MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
4Maxim Integrated
TIMING CHARACTERISTICS
(V
AVDD
= V
DVDD
= 4.75V to 5.25V, f
SCLK
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
REF
= 4.096V, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
TIMING CHARACTERISTICS
(V
AVDD
= 4.75V to 5.25V, V
DVDD
= 2.7V to 5.25V, f
SCLK
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
REF
= 4.096V,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
Note 2: V
AVDD
= V
DVDD
= +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time t
ACQ
1.1
Fs
SCLK to DOUT Valid t
DO
C
DOUT
= 50pF 50 ns
CS Fall to DOUT Enable
t
DV
C
DOUT
= 50pF 80 ns
CS Rise to DOUT Disable
t
TR
C
DOUT
= 50pF 80 ns
CS Pulse Width
t
CSW
50 ns
CS Fall to SCLK Rise Setup
t
CSS
100 ns
CS Rise to SCLK Rise Hold
t
CSH
0 ns
SCLK High Pulse Width t
CH
65 ns
SCLK Low Pulse Width t
CL
65 ns
SCLK Period t
CP
208 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time t
ACQ
1.1
Fs
SCLK to DOUT Valid t
DO
C
DOUT
= 50pF 100 ns
CS Fall to DOUT Enable
t
DV
C
DOUT
= 50pF 100 ns
CS Rise to DOUT Disable
t
TR
C
DOUT
= 50pF 80 ns
CS Pulse Width
t
CSW
50 ns
CS Fall to SCLK Rise Setup
t
CSS
100 ns
CS Rise to SCLK Rise Hold
t
CSH
0 ns
SCLK High Pulse Width t
CH
65 ns
SCLK Low Pulse Width t
CL
65 ns
SCLK Period t
CP
208 ns