Datasheet

MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
16Maxim Integrated
Table 1. Detailed SSPCON Register Contents
Table 2. Detailed SSPSTAT Register Contents
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
CONTROL BIT
MAX11100
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT 7 X Write Collision Detection Bit
SSPOV BIT 6 X Receive Overflow Detect Bit
SSPEN BIT 5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 BIT 3 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects f
CLK
= f
OSC
/16.
SSPM2 BIT 2 0
SSPM1 BIT 1 0
SSPM0 BIT 0 1
CONTROL BIT
MAX11100
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP BIT 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE BIT 6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A BIT 5 X Data Address Bit
P BIT 4 X STOP Bit
S BIT 3 X START Bit
R/W BIT 2 X Read/Write Bit Information
UA BIT 1 X Update Address
BF BIT 0 X Buffer Full Status Bit
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1 D0D7 D6 D5 D4 D3 D2
2420
1612
D15 D14 D13 D12 D11 D10 D9 D8
00000000
D7
TIMING NOT TO SCALE.