Datasheet

MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

13Maxim Integrated

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling

Serial Interfaces

The MAX11100’s interface is fully compatible with SPI,

QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s

serial interface as master, so that the CPU generates the

serial clock for the MAX11100. Select a clock frequency

between 100kHz and 4.8MHz:

1) Use a general-purpose I/O line on the CPU to pull CS low.

2) Activate SCLK for a minimum of 24 clock cycles. The

serial data stream of eight leading zeros followed by

the MSB of the conversion result begins at the fall-

ing edge of CS. DOUT transitions on SCLK’s falling

edge and the output is available in MSB-first format.

Observe the SCLK to DOUT valid timing characteris-

tic. Clock data into the FP on SCLK’s rising edge.

3) Pull CS high at or after the 24th falling clock edge. If

CS remains low, trailing zeros are clocked out after

the least significant bit (D0 = LSB).

4) With CS high, wait at least 50ns (t

CSW

) before start-

ing a new conversion by pulling CS low. A conver-

sion can be aborted by pulling CS high before the

conversion ends. Wait at least 50ns before starting a

new conversion.

CLK

CHANGE MUX INPUT HERE

CONVERSION

IN1

A0 A1

IN2

IN3

IN4

OUT

ACQUISITION

4-TO-1

MUX

AIN

MAX11100