Datasheet

MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
5
Maxim Integrated
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at V
AV
DD
= V
DV
DD
= +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
ELECTRICAL CHARACTERISTICS (continued)
(V
AV
DD
= +3.0V to +3.6V, V
DV
DD
= +2.7V to V
AV
DD
, f
XIN CLOCK
= 24.576MHz, f
OUT
= 16ksps, V
REFIO
= +2.5V (external), C
REFIO
=
C
REF0
= C
REF1
= C
REF2
= C
REF3
= 1μF to AGND, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
C
LOAD
= 30pF 1.5 10 16
SCLK Rise to DOUT Valid t
DOT
C
LOAD
= 100pF < 16
ns
CS Fall to DOUT Enable t
DOE
C
LOAD
= 30pF 0.3 20 ns
CS Rise to DOUT Disable t
DOD
C
LOAD
= 30pF 0.7 16 ns
CS Pulse Width t
CSW
16 ns
CASCIN-to-SCLK Rise Setup t
SC
16 ns
SCLK Rise to CASCOUT Valid t
COT
C
LOAD
= 100pF 20 ns
SYNC Pulse Width t
SYN
2
XIN
Clock
Cycles
XIN Clock Pulse Width t
XPW
16 ns
DRDYIN to DRDYOUT t
DRDY
C
LOAD
= 30pF 20 ns
XIN Clock to DRDYOUT Delay t
XDRDY
DRDYIN = DGND 40 ns
XIN Clock Period t
XP
40 ns
XIN Clock to SYNC Setup t
SS
(Note 12) 16 ns
SYNC to XIN Clock Hold t
HS
(Note 12) 5 ns
XIN-to-CLKOUT Delay t
XCD
40 ns
Power-On Reset Delay (Note 13) < 1 ms