Datasheet

MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
AV
DD
= +3.0V to +3.6V, V
DV
DD
= +2.7V to V
AV
DD
, f
XIN CLOCK
= 24.576MHz, f
OUT
= 16ksps, V
REFIO
= +2.5V (external), C
REFIO
=
C
REF0
= C
REF1
= C
REF2
= C
REF3
= 1μF to AGND, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN)
Input Low Voltage V
IL
0.3 x
V
DVDD
V
Input High Voltage V
IH
0.7 x
V
DVDD
V
Input Hysteresis V
HYS
V
DVDD
= 3.0V 100 mV
Input Leakage Current I
L
±0.01 ±1μA
Input Capacitance C
IN
15 pF
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)
Output Low Voltage V
OL
I
SINK
= 5mA
0.15 x
V
DVDD
V
Output High Voltage V
OH
I
SOURCE
= 1mA
0.85 x
V
DVDD
V
Three-State Leakage Current I
LT
±1 μA
Three-State Capacitance C
OUT
15 pF
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT)
Output Low Voltage V
OL
I
SINK
= 5mA
0.15 x
V
DVDD
V
Output High Voltage V
OH
Internal pullup only
0.85 x
V
DVDD
V
Internal Pullup Resistance 30 kΩ
POWER REQUIREMENTS
Analog Supply Voltage AV
DD
3.0 3.6 V
Digital Supply Voltage DV
DD
2.7 V
AVDD
V
Normal operation 25 35 mA
Analog Supply Current (Note 11) I
AVDD
Shutdown and f
XINCLOCK
= 0Hz 0.1 5 μA
Normal operation 11 15 mA
Digital Supply Current (Note 11) I
DVDD
Shutdown and f
XINCLOCK
= 0Hz 0.3 μA
AC Positive-Supply Rejection V
AVDD
= 3.3V + 100mV
P-P
at 1kHz 70 dB
DC Positive-Supply Rejection V
AVDD
= V
DVDD
= 3.0V to 3.6V 75 dB
ESD PROTECTION
All Pins ESD Human Body Model 2.5 kV
TIMING CHARACTERISTICS (Figures 7–10)
SCLK Clock Period t
SCP
50 ns
SCLK Pulse Width (High and Low) t
PW
20 ns
DIN or CS to SCLK Fall Setup t
SU
10 ns
SCLK Fall to DIN Hold t
HD
0ns
SCLK Rise to CS Rise t
CSH1
0ns