Datasheet

MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
18
Maxim Integrated
Registers
The devices include four registers accessible by 7
command bytes. The command bytes provide read
and write access to the Data Rate Control register, the
Sampling Instant Control register, and the Configuration
register, and read access to the Data register. See
Table 2. Figure 9 shows the CASCIN and CASOUT
timing diagram. Figure 10 is the XIN clock, CLKOUT,
SYNC, and DRDYOUT timing diagram.
Table 2. Command Bytes
R/W
ADDRESS
[A6:A0]
DATA
LENGTH*
FUNCTION
0 1000000 32 x n** bits
Write Sampling Instant
Control Register
1 1000000 32 x n bits
Read Sampling Instant
Control Register
0 1010000 16 bits
Write Data-Rate Control
Register
1 1010000 16 bits
Read Data-Rate Control
Register
0 1100000 8 x n bits
Write Configuration
Register
1 1100000 8 x n bits
Read Configuration
Register
1 1110000 96 x n bits Read Data Register
*All data lengths are proportional to the number of cascaded
devices except for reads and writes to the Data Rate Control
register. When accessing the Data Rate Control register, the
data length is fixed at 16 bits. These 16 bits are automatically
written to all cascaded devices.
**n is the total number of cascaded devices.
SCLK
CASCOUT
(DEVICE n)
CASCIN
(DEVICE n+1)
t
SC
t
COT
Figure 9. CASCIN and CASCOUT Timing Diagram
XIN CLOCK
SYNC
CLKOUT
DRDYOUT
t
XP
t
XPW
t
XCD
t
SS
t
HS
t
XDRDY
t
SYN
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing
Diagram