Datasheet

MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
10
Maxim Integrated
Pin Description (continued)
PIN NAME FUNCTION
11, 28 DGND Digital Ground
12, 27 DVDD
Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1μF capacitor in parallel with a
0.01μF capacitor as close as possible to the device.
13 CASCIN
Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the
device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the
requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is
issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy
chaining multiple devices. See the Multiple Device Connection section for connection recommendations.
14 CASCOUT
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal
the next device in the daisy-chain to begin transferring data on the next byte. CASCOUT changes after
the rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See
the Multiple Device Connection section.
15 CS
Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT
for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a
high-impedance state.
16 SCLK
Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the
rising edge of SCLK. SCLK must idle high (CPOL = 1).
17 DIN Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK.
18 DOUT
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a
falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK.
19 FAULT
Acti ve- Low O ver vol tag e Faul t Ind i cator Outp ut. F AU LT g oes l ow w hen any anal og i np ut g oes outsi d e the faul t
thr eshol d r ang e ( b etw een V
P FT
and V
N FT
) . The F AU LT outp ut i s op en d r ai n w i th a 30kΩ i nter nal p ul l up
r esi stor , al l ow i ng w i r e- N OR functi onal i ty. S ee the Anal og Inp ut Over vol tag e and Faul t P r otecti on secti on.
20 OVRFLW
Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input
channels or when FAULT goes low. The OVRFLW output is open drain with a 30kΩ internal pullup resistor,
allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
21 CLKOUT
Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.