Datasheet
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
______________________________________________________________________________________ 15
Input Range and Protection
The full-scale analog input voltage is a product of the
reference voltage. For the devices, the input is unipolar
in the range of:
In external reference mode, drive V
REFIO
with a 3.0V to
4.25V source, resulting in a full-scale input range of
3.662V to 5.188V, respectively.
All analog inputs are fault-protected up to ±20mA. The
devices include an input clamping circuit that activates
when the input voltage at the analog input is above
(V
AVDD
+ 300mV) or below -300mV. The clamp circuit
remains high impedance while the input signal is within
the range of 0V to +V
AVDD
and draws little to no cur-
rent. However, when the input signal exceeds the range
of 0V to +V
AVDD
, the clamps begin to turn on.
Consequently, to obtain the highest accuracy, ensure
that the input voltage does not exceed the range of 0V
to +V
AVDD
.
To make use of the input clamps, connect a resistor
(R
S
) between the analog input and the voltage source
to limit the voltage at the analog input so that the fault
current into the devices does not exceed ±20mA. Note
that the voltage at the analog input pin limits to approxi-
mately 7V during a fault condition so the following
equation can be used to calculate the value of R
S
:
where V
FAULT_MAX
is the maximum voltage that the
source produces during a fault condition.
R
VV
mA
S
FAULT MAX
=
−
_
7
20
0
50
4 096
to V x
REFIO
+
.
.
MAX11047/MAX11048/MAX11049/
MAX11057/MAX11058/MAX11059
CLAMP
S/H
16-/14-BIT ADC
CLAMP S/H
16-/14-BIT ADC
REF
BUF
CONFIGURATION
REGISTERS
INTERFACE
AND
CONTROL
BANDGAP
REFERENCE
8 x 16-/14-BIT REGISTERS
BIDIRECTIONAL DRIVERS
CH0
SOURCE
AVDD
AGNDS
*CONNECTED INTERNALLY ON THE TQFN PARTS
**MAX11047/MAX11048/MAX11049
†
MAX11049/MAX11059
AGND
CH7
†
DB15**
DB0/CR0
DB3/CR3
DB4
EOCb
SHDN
CONVST
CSb
RDb
WRb
DGND
DVDD
RDC
RDC_SENSE*
REFIO
INT REF
10kΩ
EXT REF
R
S
INPUT
SIGNAL
PIN
VOLTAGE
Figure 1. Required Setup for Clamp Circuit