Datasheet
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
25
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
TOP VIEW
MAX11044
MAX11044B
MAX11045
MAX11045B
MAX11046
MAX11046B
MAX11044
MAX11044B
MAX11045
MAX11045B
MAX11046
MAX11046B
TQFN
8mm x 8mm
+
15
17
16
18
19
20
21
22
23
24
25
26
27
28
DB1/CR1
*EP
DB0/CR0
EOC
CONVST
SHDN
DVDD
DGND
RDC
AGNDS
AVDD
AGND
CH0*/I.C.
†‡
AGNDS
RDC
DB14
DB15
RD
CS
WR
DVDD
DGND
RDC
AGNDS
AVDD
AGND
I.C.
†‡
/CH7*
‡
MAX11044
†
MAX11045
*MAX11046
AGNDS
RDC
48
47
46
45
44
43
54
53
56
55
52
51
50
49
1 2 3 4 5 6 7 8 91011121314
42 41 40 39 38 37 36 35 34 33 32 31 30 29
DB4
CR3/DB3
CR2/DB2
DB5
DB6
DB7
DVDD
DGND
DB8
DB9
DB10
DB11
DB12
DB13
AGND
AVDD
CH1*/CH0
†
/I.C.
‡
CH2*/CH1
†
/CH0
‡
AGNDS
CH3*/CH2
†
/CH1
‡
RDC
REFIO
CH4*/CH3
†
/CH2
‡
AGNDS
CH5*/CH4
†
/CH3
‡
AGND
AVDD
CH6*/CH5
†
/I.C.
‡
TQFP
10mm x 10mm
+
19
21
20
22
23
24
25
26
27
28
29
30
31
32
*EP
EOC
CONVST
SHDN
DVDD
DGND
AGNDS
AVDD
AGND
RDC_SENSE
RDC
AGNDS
AVDD
AGND
CH0*/I.C.
†‡
AGNDS
DGND
AGNDS
RD
CS
WR
AVDD
AGND
RDC_SENSE
RDC
AGNDS
AVDD
AGND
I.C.
†‡
/CH7*
AGNDS
54
53
52
51
50
49
60
59
62
61
58
57
56
55
1 2 3 4 5 6 7 8 91011121314
48 47 46 45 44 43 42 41 40 39 38 37 36 35
DB5
DB4
CR3/DB3
DB6
DB7
DVDD
DGND
DB8
DB9
DB10
DB11
DB12
DB13
DB14
CH2*/CH1
†
/CH0
‡
AGND
AVDD
AGNDS
CH3*/CH2
†
/CH1
‡
RDC
REFIO
CH4*/CH3
†
/CH2
‡
AGNDS
CH5*/CH4
†
/CH3
‡
AGND
AVDD
CH6*/CH5
†
/I.C.
‡
RDC
15 16
CR2/DB2
CR1/DB1
34 33
CH1*/CH0
†
/I.C.
‡
RDC
17
18
DB0/CR0DB15
DVDD
64
63
Pin Configurations
Positive Full-Scale Error
The error in the input voltage that causes the last code
transition of FFFE to FFFF (hex) for 16-bit or 3FFE to 3FFF
(hex) for 14-bit devices (in default offset binary mode) or
7FFE to 7FFF (hex) for 16-bit or 1FFE to 1FFF (hex) for 14-
bit devices (in two’s complement mode) from the ideal
input voltage of 32,766.5 x (10/4.096) x (V
REF
/65,536) for
16-bit or 8190.5 x (10/4.096) x (V
REF
/16,384) for 14-bit
devices after correction for offset error.
Negative Full-Scale Error
The error in the input voltage that causes the first code
transition of 0000 to 0001 (hex) (in default offset binary
mode) or 8000 to 8001 (hex) for 16-bit or 2000 to 2001
(hex) for 14-bit devices (in two’s complement mode) from
the ideal input voltage of -32,767.5 x (10/4.096) x
(V
REF
/65,536) for 16-bit or -8191.5 x (10/4.096) x
(V
REF
/16,384) for 14-bit devices after correction for offset
error.