Datasheet

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
16
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
an internal bandgap reference circuit (V
REFIO
=
4.096V). Drive REFIO with an external reference or
bypass with 0.1μF capacitor to ground when using the
internal reference.
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
Input Range and Protection
The full-scale analog input voltage is a product of the ref-
erence voltage. For the MAX11044/MAX11044B/
MAX11045/MAX11045B/MAX11046/MAX11046B and
MAX11054/MAX11055/MAX11056, the full-scale input is
bipolar in the range of:
When in external reference mode, drive V
REFIO
with a
3.0V to 4.25V source, resulting in an input range of
±3.662V to ±5.188V, respectively.
All analog inputs are fault-protected to up to ±20mA. The
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 include an input clamping circuit that acti-
vates when the input voltage at the analog input is
above (V
AVDD
+ 300mV) or below –(V
AVDD
+ 300mV).
The clamp circuit remains high impedance while the
input signal is within the range of ±V
AVDD
and draws lit-
tle or almost no current. However, when the input signal
exceeds ±V
AVDD
, the clamps begin to turn on and
shunt current to/from the AVDD supply. Consequently,
to obtain the highest accuracy, ensure that the input
voltage does not exceed ±(V
AVDD
+ 0.3V).
To make use of the input clamps (see Figure 1), con-
nect a resistor (R
S
) between the analog input and the
voltage source to limit the voltage at the analog input so
that the fault current into the MAX11044/MAX11044B/
MAX11045/MAX11045B/MAX11046/MAX11046B and
MAX11054/MAX11055/MAX11056 does not exceed
±20mA. Note that the voltage at the analog input pin limits
to approximately 7V during a fault condition so the follow-
ing equation can be used to calculate the value of R
S
:
±(
.
)Vx
REFIO
5
4 096
MAX11044/MAX11044B/
MAX11045/MAX11045B/
MAX11046/MAX11046B
MAX11054/MAX11055/MAX11056
CLAMP
S/H
16-/14-BIT ADC
CLAMP S/H
16-/14-BIT ADC
REF
BUF
CONFIGURATION
REGISTERS
INTERFACE
AND
CONTROL
BANDGAP
REFERENCE
8 x 16-/14-BIT REGISTERS
BIDIRECTIONAL DRIVERS
CH0
SOURCE
AVDD
AGNDS
*CONNECTED INTERNALLY ON THE TQFN PARTS TO RDC
**MAX11044/MAX11045/MAX11046
†
MAX11046/MAX11056
AGND
CH7
†
DB15**
DB0/CR0
DB3/CR3
DB4
EOC
SHDN
CONVST
CS
RD
WR
DGND
DVDD
RDC
RDC_SENSE*
REFIO
INT REF
10kΩ
EXT REF
R
S
INPUT
SIGNAL
PIN
VOLTAGE
Figure 1. Required Setup for Clamp Circuit