Datasheet

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
15
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
Detailed Description
The MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/ MAX11055/
MAX11056 are fast, low-power ADCs that combine 4, 6, or 8
independent ADC channels in a single IC. Each channel
includes simultaneously sampling independent T/H circuitry
that preserves relative phase information between inputs
making the MAX11044/MAX11044B/MAX11045/
MAX11045B/MAX11046/MAX11046B and MAX11054/
MAX11055/MAX11056 ideal for motor control and power
monitoring. The MAX11044/MAX11044B/MAX11045/
MAX11045B/MAX11046/MAX11046B and MAX11054/
MAX11055/MAX11056 are available with ±5V input
ranges that feature ±20mA overrange, fault-tolerant inputs.
The MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 operate with a single 4.75V to 5.25V supply. A
separate 2.7V to 5.25V supply for digital circuitry makes
the devices compatible with low-voltage processors.
The MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 perform conversions for all channels in par-
allel by activating independent ADCs. Results are avail-
able through a high-speed, 20MHz, parallel data bus
after a conversion time of 3μs following the end of a
sample. The data bus is bidirectional and allows for
easy programming of the configuration register. The
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 feature a reference buffer, which is driven by
Pin Description (continued)
PIN
MAX11054
(TQFP-EP)
MAX11055
(TQFP-EP)
MAX11056
(TQFP-EP)
NAME FUNCTION
27, 33, 40, 48,
54
27, 33, 40, 48,
54
27, 33, 40, 48,
54
RDC
Refer ence Buffer D ecoup l i ng . C onnect al l RD C outp uts
tog ether . Byp ass to AG N D w i th at l east an 80μF total
cap aci tance. S ee the Layout, Gr ound i ng , and Byp assi ng
secti on.
37 34 31 CH0 Channel 0 Analog Input
39 37 34 CH1 Channel 1 Analog Input
42 39 37 CH2 Channel 2 Analog Input
44 42 39 CH3 Channel 3 Analog Input
41 41 41 REFIO
External Reference Input/Internal Reference Output.
Place a 0.1μF capacitor from REFIO to AGND.
— 44 42 CH4 Channel 4 Analog Input
— 47 44 CH5 Channel 5 Analog Input
— — 47 CH6 Channel 6 Analog Input
— — 50 CH7 Channel 7 Analog Input
61 61 61 WR
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
62 62 62 CS
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
63 63 63 RD
Acti ve- Low Read Inp ut. D r i ve RD l ow to r ead fr om the
AD C . E ach r i si ng ed g e of RD ad vances the channel
outp ut on the d ata b us.
64 64 64 DB13 14-Bit Parallel Data Bus Digital Output Bit 13
31, 34, 47, 50 31, 50 — I.C. Internally Connected. Connect to AGND.
———EP
E xp osed P ad . Inter nal l y connected to AG N D . C onnect to
a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance.
N ot i ntend ed as an el ectr i cal connecti on p oi nt.