Datasheet

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
14
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
Pin Description (continued)
PIN
MAX11054
(TQFP-EP)
MAX11055
(TQFP-EP)
MAX11056
(TQFP-EP)
NAME FUNCTION
1 1 1 DB12 14-Bit Parallel Data Bus Digital Output Bit 12
2 2 2 DB11 14-Bit Parallel Data Bus Digital Output Bit 11
3 3 3 DB10 14-Bit Parallel Data Bus Digital Output Bit 10
4 4 4 DB9 14-Bit Parallel Data Bus Digital Output Bit 9
5 5 5 DB8 14-Bit Parallel Data Bus Digital Output Bit 8
6 6 6 DB7 14-Bit Parallel Data Bus Digital Output Bit 7
7 7 7 DB6 14-Bit Parallel Data Bus Digital Output Bit 6
8, 22, 59 8, 22, 59 8, 22, 59 DGND Digital Ground
9, 21, 60 9, 21, 60 9, 21, 60 DVDD
Digital Supply. Bypass to DGND with a 0.1μF capacitor
at each DVDD input.
10 10 10 DB5 14-Bit Parallel Data Bus Digital Output Bit 5
11 11 11 DB4 14-Bit Parallel Data Bus Digital Output Bit 4
12 12 12 DB3 14-Bit Parallel Data Bus Digital Output Bit 3
13 13 13 DB2 14-Bit Parallel Data Bus Digital Output Bit 2
14 14 14 DB1/CR3
14-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 3
15 15 15 DB0/CR2
14-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 2
16 16 16 CR1 Configuration Register Input Bit 1
17 17 17 CR0 Configuration Register Input Bit 0
18 18 18 EOC
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
19 19 19 CONVST
C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s
sam p l e and star ts a conver si on on the cap tur ed sam p l e.
The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow
and C ON V S T m od e = 0.
20 20 20 SHDN
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
AVDD
Analog Supply Input. Bypass AVDD to AGND with a
0.1μF capacitor at each AVDD input.
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
AGND Analog Ground. Connect all AGND inputs together.
26, 55 26, 55 26, 55 RDC_SENSE Refer ence Buffer S ense Feed b ack. C onnect to RD C p l ane.